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[chore]: Bump github.com/minio/minio-go/v7 from 7.0.48 to 7.0.49 (#1567)
Bumps [github.com/minio/minio-go/v7](https://github.com/minio/minio-go) from 7.0.48 to 7.0.49. - [Release notes](https://github.com/minio/minio-go/releases) - [Commits](https://github.com/minio/minio-go/compare/v7.0.48...v7.0.49) --- updated-dependencies: - dependency-name: github.com/minio/minio-go/v7 dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] <support@github.com> Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
This commit is contained in:
dependabot[bot]
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38 changed files with 1696 additions and 1023 deletions
229
vendor/github.com/klauspost/cpuid/v2/README.md
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vendor/github.com/klauspost/cpuid/v2/README.md
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@ -16,10 +16,17 @@ Package home: https://github.com/klauspost/cpuid
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## installing
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`go get -u github.com/klauspost/cpuid/v2` using modules.
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`go get -u github.com/klauspost/cpuid/v2` using modules.
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Drop `v2` for others.
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### Homebrew
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For macOS/Linux users, you can install via [brew](https://brew.sh/)
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```sh
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$ brew install cpuid
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```
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## example
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```Go
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@ -77,10 +84,14 @@ We have Streaming SIMD 2 Extensions
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The `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features.
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A faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler.
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To test a larger number of features, they can be combined using `f := CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)`, etc.
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This can be using with `cpuid.CPU.HasAll(f)` to quickly test if all features are supported.
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Note that for some cpu/os combinations some features will not be detected.
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`amd64` has rather good support and should work reliably on all platforms.
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Note that hypervisors may not pass through all CPU features.
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Note that hypervisors may not pass through all CPU features through to the guest OS,
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so even if your host supports a feature it may not be visible on guests.
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## arm64 feature detection
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@ -253,6 +264,218 @@ Exit Code 0
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Exit Code 1
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```
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## Available flags
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### x86 & amd64
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| Feature Flag | Description |
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|--------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| ADX | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) |
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| AESNI | Advanced Encryption Standard New Instructions |
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| AMD3DNOW | AMD 3DNOW |
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| AMD3DNOWEXT | AMD 3DNowExt |
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| AMXBF16 | Tile computational operations on BFLOAT16 numbers |
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| AMXINT8 | Tile computational operations on 8-bit integers |
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| AMXFP16 | Tile computational operations on FP16 numbers |
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| AMXTILE | Tile architecture |
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| AVX | AVX functions |
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| AVX2 | AVX2 functions |
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| AVX512BF16 | AVX-512 BFLOAT16 Instructions |
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| AVX512BITALG | AVX-512 Bit Algorithms |
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| AVX512BW | AVX-512 Byte and Word Instructions |
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| AVX512CD | AVX-512 Conflict Detection Instructions |
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| AVX512DQ | AVX-512 Doubleword and Quadword Instructions |
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| AVX512ER | AVX-512 Exponential and Reciprocal Instructions |
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| AVX512F | AVX-512 Foundation |
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| AVX512FP16 | AVX-512 FP16 Instructions |
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| AVX512IFMA | AVX-512 Integer Fused Multiply-Add Instructions |
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| AVX512PF | AVX-512 Prefetch Instructions |
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| AVX512VBMI | AVX-512 Vector Bit Manipulation Instructions |
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| AVX512VBMI2 | AVX-512 Vector Bit Manipulation Instructions, Version 2 |
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| AVX512VL | AVX-512 Vector Length Extensions |
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| AVX512VNNI | AVX-512 Vector Neural Network Instructions |
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| AVX512VP2INTERSECT | AVX-512 Intersect for D/Q |
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| AVX512VPOPCNTDQ | AVX-512 Vector Population Count Doubleword and Quadword |
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| AVXIFMA | AVX-IFMA instructions |
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| AVXNECONVERT | AVX-NE-CONVERT instructions |
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| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |
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| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |
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| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |
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| BMI1 | Bit Manipulation Instruction Set 1 |
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| BMI2 | Bit Manipulation Instruction Set 2 |
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| CETIBT | Intel CET Indirect Branch Tracking |
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| CETSS | Intel CET Shadow Stack |
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| CLDEMOTE | Cache Line Demote |
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| CLMUL | Carry-less Multiplication |
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| CLZERO | CLZERO instruction supported |
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| CMOV | i686 CMOV |
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| CMPCCXADD | CMPCCXADD instructions |
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| CMPSB_SCADBS_SHORT | Fast short CMPSB and SCASB |
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| CMPXCHG8 | CMPXCHG8 instruction |
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| CPBOOST | Core Performance Boost |
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| CPPC | AMD: Collaborative Processor Performance Control |
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| CX16 | CMPXCHG16B Instruction |
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| EFER_LMSLE_UNS | AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ |
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| ENQCMD | Enqueue Command |
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| ERMS | Enhanced REP MOVSB/STOSB |
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| F16C | Half-precision floating-point conversion |
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| FLUSH_L1D | Flush L1D cache |
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| FMA3 | Intel FMA 3. Does not imply AVX. |
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| FMA4 | Bulldozer FMA4 functions |
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| FP128 | AMD: When set, the internal FP/SIMD execution datapath is 128-bits wide |
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| FP256 | AMD: When set, the internal FP/SIMD execution datapath is 256-bits wide |
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| FSRM | Fast Short Rep Mov |
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| FXSR | FXSAVE, FXRESTOR instructions, CR4 bit 9 |
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| FXSROPT | FXSAVE/FXRSTOR optimizations |
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| GFNI | Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. |
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| HLE | Hardware Lock Elision |
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| HRESET | If set CPU supports history reset and the IA32_HRESET_ENABLE MSR |
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| HTT | Hyperthreading (enabled) |
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| HWA | Hardware assert supported. Indicates support for MSRC001_10 |
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| HYBRID_CPU | This part has CPUs of more than one type. |
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| HYPERVISOR | This bit has been reserved by Intel & AMD for use by hypervisors |
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| IA32_ARCH_CAP | IA32_ARCH_CAPABILITIES MSR (Intel) |
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| IA32_CORE_CAP | IA32_CORE_CAPABILITIES MSR |
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| IBPB | Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) |
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| IBRS | AMD: Indirect Branch Restricted Speculation |
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| IBRS_PREFERRED | AMD: IBRS is preferred over software solution |
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| IBRS_PROVIDES_SMP | AMD: IBRS provides Same Mode Protection |
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| IBS | Instruction Based Sampling (AMD) |
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| IBSBRNTRGT | Instruction Based Sampling Feature (AMD) |
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| IBSFETCHSAM | Instruction Based Sampling Feature (AMD) |
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| IBSFFV | Instruction Based Sampling Feature (AMD) |
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| IBSOPCNT | Instruction Based Sampling Feature (AMD) |
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| IBSOPCNTEXT | Instruction Based Sampling Feature (AMD) |
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| IBSOPSAM | Instruction Based Sampling Feature (AMD) |
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| IBSRDWROPCNT | Instruction Based Sampling Feature (AMD) |
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| IBSRIPINVALIDCHK | Instruction Based Sampling Feature (AMD) |
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| IBS_FETCH_CTLX | AMD: IBS fetch control extended MSR supported |
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| IBS_OPDATA4 | AMD: IBS op data 4 MSR supported |
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| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |
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| IBS_PREVENTHOST | Disallowing IBS use by the host supported |
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| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |
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| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |
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| INVLPGB | NVLPGB and TLBSYNC instruction supported |
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| LAHF | LAHF/SAHF in long mode |
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| LAM | If set, CPU supports Linear Address Masking |
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| LBRVIRT | LBR virtualization |
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| LZCNT | LZCNT instruction |
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| MCAOVERFLOW | MCA overflow recovery support. |
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| MCDT_NO | Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. |
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| MCOMMIT | MCOMMIT instruction supported |
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| MD_CLEAR | VERW clears CPU buffers |
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| MMX | standard MMX |
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| MMXEXT | SSE integer functions or AMD MMX ext |
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| MOVBE | MOVBE instruction (big-endian) |
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| MOVDIR64B | Move 64 Bytes as Direct Store |
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| MOVDIRI | Move Doubleword as Direct Store |
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| MOVSB_ZL | Fast Zero-Length MOVSB |
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| MPX | Intel MPX (Memory Protection Extensions) |
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| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD |
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| MSRIRC | Instruction Retired Counter MSR available |
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| MSR_PAGEFLUSH | Page Flush MSR available |
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| NRIPS | Indicates support for NRIP save on VMEXIT |
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| NX | NX (No-Execute) bit |
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| OSXSAVE | XSAVE enabled by OS |
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| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |
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| POPCNT | POPCNT instruction |
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| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |
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| PREFETCHI | PREFETCHIT0/1 instructions |
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| PSFD | AMD: Predictive Store Forward Disable |
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| RDPRU | RDPRU instruction supported |
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| RDRAND | RDRAND instruction is available |
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| RDSEED | RDSEED instruction is available |
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| RDTSCP | RDTSCP Instruction |
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| RTM | Restricted Transactional Memory |
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| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |
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| SERIALIZE | Serialize Instruction Execution |
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| SEV | AMD Secure Encrypted Virtualization supported |
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| SEV_64BIT | AMD SEV guest execution only allowed from a 64-bit host |
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| SEV_ALTERNATIVE | AMD SEV Alternate Injection supported |
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| SEV_DEBUGSWAP | Full debug state swap supported for SEV-ES guests |
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| SEV_ES | AMD SEV Encrypted State supported |
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| SEV_RESTRICTED | AMD SEV Restricted Injection supported |
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| SEV_SNP | AMD SEV Secure Nested Paging supported |
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| SGX | Software Guard Extensions |
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| SGXLC | Software Guard Extensions Launch Control |
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| SHA | Intel SHA Extensions |
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| SME | AMD Secure Memory Encryption supported |
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| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced |
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| SPEC_CTRL_SSBD | Speculative Store Bypass Disable |
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| SRBDS_CTRL | SRBDS mitigation MSR available |
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| SSE | SSE functions |
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| SSE2 | P4 SSE functions |
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| SSE3 | Prescott SSE3 functions |
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| SSE4 | Penryn SSE4.1 functions |
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| SSE42 | Nehalem SSE4.2 functions |
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| SSE4A | AMD Barcelona microarchitecture SSE4a instructions |
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| SSSE3 | Conroe SSSE3 functions |
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| STIBP | Single Thread Indirect Branch Predictors |
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| STIBP_ALWAYSON | AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On |
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| STOSB_SHORT | Fast short STOSB |
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| SUCCOR | Software uncorrectable error containment and recovery capability. |
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| SVM | AMD Secure Virtual Machine |
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| SVMDA | Indicates support for the SVM decode assists. |
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| SVMFBASID | SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control |
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| SVML | AMD SVM lock. Indicates support for SVM-Lock. |
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| SVMNP | AMD SVM nested paging |
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| SVMPF | SVM pause intercept filter. Indicates support for the pause intercept filter |
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| SVMPFT | SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold |
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| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. |
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| SYSEE | SYSENTER and SYSEXIT instructions |
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| TBM | AMD Trailing Bit Manipulation |
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| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations |
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| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |
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| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. |
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| TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 |
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| TSXLDTRK | Intel TSX Suspend Load Address Tracking |
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| VAES | Vector AES. AVX(512) versions requires additional checks. |
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| VMCBCLEAN | VMCB clean bits. Indicates support for VMCB clean bits. |
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| VMPL | AMD VM Permission Levels supported |
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| VMSA_REGPROT | AMD VMSA Register Protection supported |
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| VMX | Virtual Machine Extensions |
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| VPCLMULQDQ | Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. |
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| VTE | AMD Virtual Transparent Encryption supported |
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| WAITPKG | TPAUSE, UMONITOR, UMWAIT |
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| WBNOINVD | Write Back and Do Not Invalidate Cache |
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| X87 | FPU |
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| XGETBV1 | Supports XGETBV with ECX = 1 |
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| XOP | Bulldozer XOP functions |
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| XSAVE | XSAVE, XRESTOR, XSETBV, XGETBV |
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| XSAVEC | Supports XSAVEC and the compacted form of XRSTOR. |
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| XSAVEOPT | XSAVEOPT available |
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| XSAVES | Supports XSAVES/XRSTORS and IA32_XSS |
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# ARM features:
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| Feature Flag | Description |
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|--------------|------------------------------------------------------------------|
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| AESARM | AES instructions |
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| ARMCPUID | Some CPU ID registers readable at user-level |
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| ASIMD | Advanced SIMD |
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| ASIMDDP | SIMD Dot Product |
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| ASIMDHP | Advanced SIMD half-precision floating point |
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| ASIMDRDM | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) |
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| ATOMICS | Large System Extensions (LSE) |
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| CRC32 | CRC32/CRC32C instructions |
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| DCPOP | Data cache clean to Point of Persistence (DC CVAP) |
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| EVTSTRM | Generic timer |
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| FCMA | Floatin point complex number addition and multiplication |
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| FP | Single-precision and double-precision floating point |
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| FPHP | Half-precision floating point |
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| GPA | Generic Pointer Authentication |
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| JSCVT | Javascript-style double->int convert (FJCVTZS) |
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| LRCPC | Weaker release consistency (LDAPR, etc) |
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| PMULL | Polynomial Multiply instructions (PMULL/PMULL2) |
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| SHA1 | SHA-1 instructions (SHA1C, etc) |
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| SHA2 | SHA-2 instructions (SHA256H, etc) |
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| SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) |
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| SHA512 | SHA512 instructions |
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| SM3 | SM3 instructions |
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| SM4 | SM4 instructions |
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| SVE | Scalable Vector Extension |
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# license
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||||
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This code is published under an MIT license. See LICENSE file for more information.
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|
|
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146
vendor/github.com/klauspost/cpuid/v2/cpuid.go
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@ -73,6 +73,7 @@ const (
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AMD3DNOW // AMD 3DNOW
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AMD3DNOWEXT // AMD 3DNowExt
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AMXBF16 // Tile computational operations on BFLOAT16 numbers
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AMXFP16 // Tile computational operations on FP16 numbers
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||||
AMXINT8 // Tile computational operations on 8-bit integers
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AMXTILE // Tile architecture
|
||||
AVX // AVX functions
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@ -93,8 +94,11 @@ const (
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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||||
AVXIFMA // AVX-IFMA instructions
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||||
AVXNECONVERT // AVX-NE-CONVERT instructions
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||||
AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
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||||
AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
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||||
AVXVNNIINT8 // AVX-VNNI-INT8 instructions
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||||
BMI1 // Bit Manipulation Instruction Set 1
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||||
BMI2 // Bit Manipulation Instruction Set 2
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||||
CETIBT // Intel CET Indirect Branch Tracking
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||||
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@ -103,15 +107,22 @@ const (
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CLMUL // Carry-less Multiplication
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CLZERO // CLZERO instruction supported
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CMOV // i686 CMOV
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||||
CMPCCXADD // CMPCCXADD instructions
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||||
CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
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||||
CMPXCHG8 // CMPXCHG8 instruction
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||||
CPBOOST // Core Performance Boost
|
||||
CPPC // AMD: Collaborative Processor Performance Control
|
||||
CX16 // CMPXCHG16B Instruction
|
||||
EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
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||||
ENQCMD // Enqueue Command
|
||||
ERMS // Enhanced REP MOVSB/STOSB
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||||
F16C // Half-precision floating-point conversion
|
||||
FLUSH_L1D // Flush L1D cache
|
||||
FMA3 // Intel FMA 3. Does not imply AVX.
|
||||
FMA4 // Bulldozer FMA4 functions
|
||||
FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
|
||||
FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
|
||||
FSRM // Fast Short Rep Mov
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||||
FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
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||||
FXSROPT // FXSAVE/FXRSTOR optimizations
|
||||
GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
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||||
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|
@ -119,8 +130,14 @@ const (
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|||
HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
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||||
HTT // Hyperthreading (enabled)
|
||||
HWA // Hardware assert supported. Indicates support for MSRC001_10
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||||
HYBRID_CPU // This part has CPUs of more than one type.
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||||
HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
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||||
IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
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IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
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||||
IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
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||||
IBRS // AMD: Indirect Branch Restricted Speculation
|
||||
IBRS_PREFERRED // AMD: IBRS is preferred over software solution
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||||
IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
|
||||
IBS // Instruction Based Sampling (AMD)
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||||
IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
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||||
IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
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||||
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|
@ -130,7 +147,11 @@ const (
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IBSOPSAM // Instruction Based Sampling Feature (AMD)
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||||
IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
|
||||
IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
|
||||
IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
|
||||
IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
|
||||
IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
|
||||
IBS_PREVENTHOST // Disallowing IBS use by the host supported
|
||||
IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
|
||||
INT_WBINVD // WBINVD/WBNOINVD are interruptible.
|
||||
INVLPGB // NVLPGB and TLBSYNC instruction supported
|
||||
LAHF // LAHF/SAHF in long mode
|
||||
|
|
@ -138,13 +159,16 @@ const (
|
|||
LBRVIRT // LBR virtualization
|
||||
LZCNT // LZCNT instruction
|
||||
MCAOVERFLOW // MCA overflow recovery support.
|
||||
MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
|
||||
MCOMMIT // MCOMMIT instruction supported
|
||||
MD_CLEAR // VERW clears CPU buffers
|
||||
MMX // standard MMX
|
||||
MMXEXT // SSE integer functions or AMD MMX ext
|
||||
MOVBE // MOVBE instruction (big-endian)
|
||||
MOVDIR64B // Move 64 Bytes as Direct Store
|
||||
MOVDIRI // Move Doubleword as Direct Store
|
||||
MOVSB_ZL // Fast Zero-Length MOVSB
|
||||
MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
|
||||
MPX // Intel MPX (Memory Protection Extensions)
|
||||
MSRIRC // Instruction Retired Counter MSR available
|
||||
MSR_PAGEFLUSH // Page Flush MSR available
|
||||
|
|
@ -153,6 +177,9 @@ const (
|
|||
OSXSAVE // XSAVE enabled by OS
|
||||
PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
|
||||
POPCNT // POPCNT instruction
|
||||
PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
|
||||
PREFETCHI // PREFETCHIT0/1 instructions
|
||||
PSFD // AMD: Predictive Store Forward Disable
|
||||
RDPRU // RDPRU instruction supported
|
||||
RDRAND // RDRAND instruction is available
|
||||
RDSEED // RDSEED instruction is available
|
||||
|
|
@ -172,6 +199,8 @@ const (
|
|||
SHA // Intel SHA Extensions
|
||||
SME // AMD Secure Memory Encryption supported
|
||||
SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
|
||||
SPEC_CTRL_SSBD // Speculative Store Bypass Disable
|
||||
SRBDS_CTRL // SRBDS mitigation MSR available
|
||||
SSE // SSE functions
|
||||
SSE2 // P4 SSE functions
|
||||
SSE3 // Prescott SSE3 functions
|
||||
|
|
@ -180,6 +209,7 @@ const (
|
|||
SSE4A // AMD Barcelona microarchitecture SSE4a instructions
|
||||
SSSE3 // Conroe SSSE3 functions
|
||||
STIBP // Single Thread Indirect Branch Predictors
|
||||
STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
|
||||
STOSB_SHORT // Fast short STOSB
|
||||
SUCCOR // Software uncorrectable error containment and recovery capability.
|
||||
SVM // AMD Secure Virtual Machine
|
||||
|
|
@ -192,8 +222,9 @@ const (
|
|||
SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
|
||||
SYSEE // SYSENTER and SYSEXIT instructions
|
||||
TBM // AMD Trailing Bit Manipulation
|
||||
TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||
TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
|
||||
TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
|
||||
TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||
TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
|
||||
TSXLDTRK // Intel TSX Suspend Load Address Tracking
|
||||
VAES // Vector AES. AVX(512) versions requires additional checks.
|
||||
|
|
@ -358,7 +389,7 @@ func (c CPUInfo) Supports(ids ...FeatureID) bool {
|
|||
|
||||
// Has allows for checking a single feature.
|
||||
// Should be inlined by the compiler.
|
||||
func (c CPUInfo) Has(id FeatureID) bool {
|
||||
func (c *CPUInfo) Has(id FeatureID) bool {
|
||||
return c.featureSet.inSet(id)
|
||||
}
|
||||
|
||||
|
|
@ -372,26 +403,47 @@ func (c CPUInfo) AnyOf(ids ...FeatureID) bool {
|
|||
return false
|
||||
}
|
||||
|
||||
// Features contains several features combined for a fast check using
|
||||
// CpuInfo.HasAll
|
||||
type Features *flagSet
|
||||
|
||||
// CombineFeatures allows to combine several features for a close to constant time lookup.
|
||||
func CombineFeatures(ids ...FeatureID) Features {
|
||||
var v flagSet
|
||||
for _, id := range ids {
|
||||
v.set(id)
|
||||
}
|
||||
return &v
|
||||
}
|
||||
|
||||
func (c *CPUInfo) HasAll(f Features) bool {
|
||||
return c.featureSet.hasSetP(f)
|
||||
}
|
||||
|
||||
// https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
|
||||
var level1Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)
|
||||
var level2Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3)
|
||||
var level3Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE)
|
||||
var level4Features = flagSetWith(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL)
|
||||
var oneOfLevel = CombineFeatures(SYSEE, SYSCALL)
|
||||
var level1Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2)
|
||||
var level2Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3)
|
||||
var level3Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE)
|
||||
var level4Features = CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SSE, SSE2, CX16, LAHF, POPCNT, SSE3, SSE4, SSE42, SSSE3, AVX, AVX2, BMI1, BMI2, F16C, FMA3, LZCNT, MOVBE, OSXSAVE, AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL)
|
||||
|
||||
// X64Level returns the microarchitecture level detected on the CPU.
|
||||
// If features are lacking or non x64 mode, 0 is returned.
|
||||
// See https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels
|
||||
func (c CPUInfo) X64Level() int {
|
||||
if c.featureSet.hasSet(level4Features) {
|
||||
if !c.featureSet.hasOneOf(oneOfLevel) {
|
||||
return 0
|
||||
}
|
||||
if c.featureSet.hasSetP(level4Features) {
|
||||
return 4
|
||||
}
|
||||
if c.featureSet.hasSet(level3Features) {
|
||||
if c.featureSet.hasSetP(level3Features) {
|
||||
return 3
|
||||
}
|
||||
if c.featureSet.hasSet(level2Features) {
|
||||
if c.featureSet.hasSetP(level2Features) {
|
||||
return 2
|
||||
}
|
||||
if c.featureSet.hasSet(level1Features) {
|
||||
if c.featureSet.hasSetP(level1Features) {
|
||||
return 1
|
||||
}
|
||||
return 0
|
||||
|
|
@ -555,7 +607,7 @@ const flagMask = flagBits - 1
|
|||
// flagSet contains detected cpu features and characteristics in an array of flags
|
||||
type flagSet [(lastID + flagMask) / flagBits]flags
|
||||
|
||||
func (s flagSet) inSet(feat FeatureID) bool {
|
||||
func (s *flagSet) inSet(feat FeatureID) bool {
|
||||
return s[feat>>flagBitsLog2]&(1<<(feat&flagMask)) != 0
|
||||
}
|
||||
|
||||
|
|
@ -585,7 +637,7 @@ func (s *flagSet) or(other flagSet) {
|
|||
}
|
||||
|
||||
// hasSet returns whether all features are present.
|
||||
func (s flagSet) hasSet(other flagSet) bool {
|
||||
func (s *flagSet) hasSet(other flagSet) bool {
|
||||
for i, v := range other[:] {
|
||||
if s[i]&v != v {
|
||||
return false
|
||||
|
|
@ -594,8 +646,28 @@ func (s flagSet) hasSet(other flagSet) bool {
|
|||
return true
|
||||
}
|
||||
|
||||
// hasSet returns whether all features are present.
|
||||
func (s *flagSet) hasSetP(other *flagSet) bool {
|
||||
for i, v := range other[:] {
|
||||
if s[i]&v != v {
|
||||
return false
|
||||
}
|
||||
}
|
||||
return true
|
||||
}
|
||||
|
||||
// hasOneOf returns whether one or more features are present.
|
||||
func (s *flagSet) hasOneOf(other *flagSet) bool {
|
||||
for i, v := range other[:] {
|
||||
if s[i]&v != 0 {
|
||||
return true
|
||||
}
|
||||
}
|
||||
return false
|
||||
}
|
||||
|
||||
// nEnabled will return the number of enabled flags.
|
||||
func (s flagSet) nEnabled() (n int) {
|
||||
func (s *flagSet) nEnabled() (n int) {
|
||||
for _, v := range s[:] {
|
||||
n += bits.OnesCount64(uint64(v))
|
||||
}
|
||||
|
|
@ -1093,21 +1165,36 @@ func support() flagSet {
|
|||
fs.setIf(ecx&(1<<30) != 0, SGXLC)
|
||||
|
||||
// CPUID.(EAX=7, ECX=0).EDX
|
||||
fs.setIf(edx&(1<<4) != 0, FSRM)
|
||||
fs.setIf(edx&(1<<9) != 0, SRBDS_CTRL)
|
||||
fs.setIf(edx&(1<<10) != 0, MD_CLEAR)
|
||||
fs.setIf(edx&(1<<11) != 0, RTM_ALWAYS_ABORT)
|
||||
fs.setIf(edx&(1<<14) != 0, SERIALIZE)
|
||||
fs.setIf(edx&(1<<15) != 0, HYBRID_CPU)
|
||||
fs.setIf(edx&(1<<16) != 0, TSXLDTRK)
|
||||
fs.setIf(edx&(1<<18) != 0, PCONFIG)
|
||||
fs.setIf(edx&(1<<20) != 0, CETIBT)
|
||||
fs.setIf(edx&(1<<26) != 0, IBPB)
|
||||
fs.setIf(edx&(1<<27) != 0, STIBP)
|
||||
fs.setIf(edx&(1<<28) != 0, FLUSH_L1D)
|
||||
fs.setIf(edx&(1<<29) != 0, IA32_ARCH_CAP)
|
||||
fs.setIf(edx&(1<<30) != 0, IA32_CORE_CAP)
|
||||
fs.setIf(edx&(1<<31) != 0, SPEC_CTRL_SSBD)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1)
|
||||
// CPUID.(EAX=7, ECX=1).EDX
|
||||
fs.setIf(edx&(1<<4) != 0, AVXVNNIINT8)
|
||||
fs.setIf(edx&(1<<5) != 0, AVXNECONVERT)
|
||||
fs.setIf(edx&(1<<14) != 0, PREFETCHI)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EAX
|
||||
eax1, _, _, _ := cpuidex(7, 1)
|
||||
fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
|
||||
fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
|
||||
fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
|
||||
fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT)
|
||||
fs.setIf(eax1&(1<<12) != 0, CMPSB_SCADBS_SHORT)
|
||||
fs.setIf(eax1&(1<<22) != 0, HRESET)
|
||||
fs.setIf(eax1&(1<<23) != 0, AVXIFMA)
|
||||
fs.setIf(eax1&(1<<26) != 0, LAM)
|
||||
|
||||
// Only detect AVX-512 features if XGETBV is supported
|
||||
|
|
@ -1145,9 +1232,15 @@ func support() flagSet {
|
|||
fs.setIf(edx&(1<<25) != 0, AMXINT8)
|
||||
// eax1 = CPUID.(EAX=7, ECX=1).EAX
|
||||
fs.setIf(eax1&(1<<5) != 0, AVX512BF16)
|
||||
fs.setIf(eax1&(1<<21) != 0, AMXFP16)
|
||||
}
|
||||
}
|
||||
|
||||
// CPUID.(EAX=7, ECX=2)
|
||||
_, _, _, edx = cpuidex(7, 2)
|
||||
fs.setIf(edx&(1<<5) != 0, MCDT_NO)
|
||||
}
|
||||
|
||||
// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
|
||||
// EAX
|
||||
// Bit 00: XSAVEOPT is available.
|
||||
|
|
@ -1212,9 +1305,21 @@ func support() flagSet {
|
|||
|
||||
if maxExtendedFunction() >= 0x80000008 {
|
||||
_, b, _, _ := cpuid(0x80000008)
|
||||
fs.setIf(b&(1<<28) != 0, PSFD)
|
||||
fs.setIf(b&(1<<27) != 0, CPPC)
|
||||
fs.setIf(b&(1<<24) != 0, SPEC_CTRL_SSBD)
|
||||
fs.setIf(b&(1<<23) != 0, PPIN)
|
||||
fs.setIf(b&(1<<21) != 0, TLB_FLUSH_NESTED)
|
||||
fs.setIf(b&(1<<20) != 0, EFER_LMSLE_UNS)
|
||||
fs.setIf(b&(1<<19) != 0, IBRS_PROVIDES_SMP)
|
||||
fs.setIf(b&(1<<18) != 0, IBRS_PREFERRED)
|
||||
fs.setIf(b&(1<<17) != 0, STIBP_ALWAYSON)
|
||||
fs.setIf(b&(1<<15) != 0, STIBP)
|
||||
fs.setIf(b&(1<<14) != 0, IBRS)
|
||||
fs.setIf((b&(1<<13)) != 0, INT_WBINVD)
|
||||
fs.setIf(b&(1<<12) != 0, IBPB)
|
||||
fs.setIf((b&(1<<9)) != 0, WBNOINVD)
|
||||
fs.setIf((b&(1<<8)) != 0, MCOMMIT)
|
||||
fs.setIf((b&(1<<13)) != 0, INT_WBINVD)
|
||||
fs.setIf((b&(1<<4)) != 0, RDPRU)
|
||||
fs.setIf((b&(1<<3)) != 0, INVLPGB)
|
||||
fs.setIf((b&(1<<1)) != 0, MSRIRC)
|
||||
|
|
@ -1235,6 +1340,13 @@ func support() flagSet {
|
|||
fs.setIf((edx>>12)&1 == 1, SVMPFT)
|
||||
}
|
||||
|
||||
if maxExtendedFunction() >= 0x8000001a {
|
||||
eax, _, _, _ := cpuid(0x8000001a)
|
||||
fs.setIf((eax>>0)&1 == 1, FP128)
|
||||
fs.setIf((eax>>1)&1 == 1, MOVU)
|
||||
fs.setIf((eax>>2)&1 == 1, FP256)
|
||||
}
|
||||
|
||||
if maxExtendedFunction() >= 0x8000001b && fs.inSet(IBS) {
|
||||
eax, _, _, _ := cpuid(0x8000001b)
|
||||
fs.setIf((eax>>0)&1 == 1, IBSFFV)
|
||||
|
|
@ -1245,6 +1357,10 @@ func support() flagSet {
|
|||
fs.setIf((eax>>5)&1 == 1, IBSBRNTRGT)
|
||||
fs.setIf((eax>>6)&1 == 1, IBSOPCNTEXT)
|
||||
fs.setIf((eax>>7)&1 == 1, IBSRIPINVALIDCHK)
|
||||
fs.setIf((eax>>8)&1 == 1, IBS_OPFUSE)
|
||||
fs.setIf((eax>>9)&1 == 1, IBS_FETCH_CTLX)
|
||||
fs.setIf((eax>>10)&1 == 1, IBS_OPDATA4) // Doc says "Fixed,0. IBS op data 4 MSR supported", but assuming they mean 1.
|
||||
fs.setIf((eax>>11)&1 == 1, IBS_ZEN4)
|
||||
}
|
||||
|
||||
if maxExtendedFunction() >= 0x8000001f && vend == AMD {
|
||||
|
|
|
|||
363
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
363
vendor/github.com/klauspost/cpuid/v2/featureid_string.go
generated
vendored
|
|
@ -13,176 +13,207 @@ func _() {
|
|||
_ = x[AMD3DNOW-3]
|
||||
_ = x[AMD3DNOWEXT-4]
|
||||
_ = x[AMXBF16-5]
|
||||
_ = x[AMXINT8-6]
|
||||
_ = x[AMXTILE-7]
|
||||
_ = x[AVX-8]
|
||||
_ = x[AVX2-9]
|
||||
_ = x[AVX512BF16-10]
|
||||
_ = x[AVX512BITALG-11]
|
||||
_ = x[AVX512BW-12]
|
||||
_ = x[AVX512CD-13]
|
||||
_ = x[AVX512DQ-14]
|
||||
_ = x[AVX512ER-15]
|
||||
_ = x[AVX512F-16]
|
||||
_ = x[AVX512FP16-17]
|
||||
_ = x[AVX512IFMA-18]
|
||||
_ = x[AVX512PF-19]
|
||||
_ = x[AVX512VBMI-20]
|
||||
_ = x[AVX512VBMI2-21]
|
||||
_ = x[AVX512VL-22]
|
||||
_ = x[AVX512VNNI-23]
|
||||
_ = x[AVX512VP2INTERSECT-24]
|
||||
_ = x[AVX512VPOPCNTDQ-25]
|
||||
_ = x[AVXSLOW-26]
|
||||
_ = x[AVXVNNI-27]
|
||||
_ = x[BMI1-28]
|
||||
_ = x[BMI2-29]
|
||||
_ = x[CETIBT-30]
|
||||
_ = x[CETSS-31]
|
||||
_ = x[CLDEMOTE-32]
|
||||
_ = x[CLMUL-33]
|
||||
_ = x[CLZERO-34]
|
||||
_ = x[CMOV-35]
|
||||
_ = x[CMPSB_SCADBS_SHORT-36]
|
||||
_ = x[CMPXCHG8-37]
|
||||
_ = x[CPBOOST-38]
|
||||
_ = x[CX16-39]
|
||||
_ = x[ENQCMD-40]
|
||||
_ = x[ERMS-41]
|
||||
_ = x[F16C-42]
|
||||
_ = x[FMA3-43]
|
||||
_ = x[FMA4-44]
|
||||
_ = x[FXSR-45]
|
||||
_ = x[FXSROPT-46]
|
||||
_ = x[GFNI-47]
|
||||
_ = x[HLE-48]
|
||||
_ = x[HRESET-49]
|
||||
_ = x[HTT-50]
|
||||
_ = x[HWA-51]
|
||||
_ = x[HYPERVISOR-52]
|
||||
_ = x[IBPB-53]
|
||||
_ = x[IBS-54]
|
||||
_ = x[IBSBRNTRGT-55]
|
||||
_ = x[IBSFETCHSAM-56]
|
||||
_ = x[IBSFFV-57]
|
||||
_ = x[IBSOPCNT-58]
|
||||
_ = x[IBSOPCNTEXT-59]
|
||||
_ = x[IBSOPSAM-60]
|
||||
_ = x[IBSRDWROPCNT-61]
|
||||
_ = x[IBSRIPINVALIDCHK-62]
|
||||
_ = x[IBS_PREVENTHOST-63]
|
||||
_ = x[INT_WBINVD-64]
|
||||
_ = x[INVLPGB-65]
|
||||
_ = x[LAHF-66]
|
||||
_ = x[LAM-67]
|
||||
_ = x[LBRVIRT-68]
|
||||
_ = x[LZCNT-69]
|
||||
_ = x[MCAOVERFLOW-70]
|
||||
_ = x[MCOMMIT-71]
|
||||
_ = x[MMX-72]
|
||||
_ = x[MMXEXT-73]
|
||||
_ = x[MOVBE-74]
|
||||
_ = x[MOVDIR64B-75]
|
||||
_ = x[MOVDIRI-76]
|
||||
_ = x[MOVSB_ZL-77]
|
||||
_ = x[MPX-78]
|
||||
_ = x[MSRIRC-79]
|
||||
_ = x[MSR_PAGEFLUSH-80]
|
||||
_ = x[NRIPS-81]
|
||||
_ = x[NX-82]
|
||||
_ = x[OSXSAVE-83]
|
||||
_ = x[PCONFIG-84]
|
||||
_ = x[POPCNT-85]
|
||||
_ = x[RDPRU-86]
|
||||
_ = x[RDRAND-87]
|
||||
_ = x[RDSEED-88]
|
||||
_ = x[RDTSCP-89]
|
||||
_ = x[RTM-90]
|
||||
_ = x[RTM_ALWAYS_ABORT-91]
|
||||
_ = x[SERIALIZE-92]
|
||||
_ = x[SEV-93]
|
||||
_ = x[SEV_64BIT-94]
|
||||
_ = x[SEV_ALTERNATIVE-95]
|
||||
_ = x[SEV_DEBUGSWAP-96]
|
||||
_ = x[SEV_ES-97]
|
||||
_ = x[SEV_RESTRICTED-98]
|
||||
_ = x[SEV_SNP-99]
|
||||
_ = x[SGX-100]
|
||||
_ = x[SGXLC-101]
|
||||
_ = x[SHA-102]
|
||||
_ = x[SME-103]
|
||||
_ = x[SME_COHERENT-104]
|
||||
_ = x[SSE-105]
|
||||
_ = x[SSE2-106]
|
||||
_ = x[SSE3-107]
|
||||
_ = x[SSE4-108]
|
||||
_ = x[SSE42-109]
|
||||
_ = x[SSE4A-110]
|
||||
_ = x[SSSE3-111]
|
||||
_ = x[STIBP-112]
|
||||
_ = x[STOSB_SHORT-113]
|
||||
_ = x[SUCCOR-114]
|
||||
_ = x[SVM-115]
|
||||
_ = x[SVMDA-116]
|
||||
_ = x[SVMFBASID-117]
|
||||
_ = x[SVML-118]
|
||||
_ = x[SVMNP-119]
|
||||
_ = x[SVMPF-120]
|
||||
_ = x[SVMPFT-121]
|
||||
_ = x[SYSCALL-122]
|
||||
_ = x[SYSEE-123]
|
||||
_ = x[TBM-124]
|
||||
_ = x[TOPEXT-125]
|
||||
_ = x[TME-126]
|
||||
_ = x[TSCRATEMSR-127]
|
||||
_ = x[TSXLDTRK-128]
|
||||
_ = x[VAES-129]
|
||||
_ = x[VMCBCLEAN-130]
|
||||
_ = x[VMPL-131]
|
||||
_ = x[VMSA_REGPROT-132]
|
||||
_ = x[VMX-133]
|
||||
_ = x[VPCLMULQDQ-134]
|
||||
_ = x[VTE-135]
|
||||
_ = x[WAITPKG-136]
|
||||
_ = x[WBNOINVD-137]
|
||||
_ = x[X87-138]
|
||||
_ = x[XGETBV1-139]
|
||||
_ = x[XOP-140]
|
||||
_ = x[XSAVE-141]
|
||||
_ = x[XSAVEC-142]
|
||||
_ = x[XSAVEOPT-143]
|
||||
_ = x[XSAVES-144]
|
||||
_ = x[AESARM-145]
|
||||
_ = x[ARMCPUID-146]
|
||||
_ = x[ASIMD-147]
|
||||
_ = x[ASIMDDP-148]
|
||||
_ = x[ASIMDHP-149]
|
||||
_ = x[ASIMDRDM-150]
|
||||
_ = x[ATOMICS-151]
|
||||
_ = x[CRC32-152]
|
||||
_ = x[DCPOP-153]
|
||||
_ = x[EVTSTRM-154]
|
||||
_ = x[FCMA-155]
|
||||
_ = x[FP-156]
|
||||
_ = x[FPHP-157]
|
||||
_ = x[GPA-158]
|
||||
_ = x[JSCVT-159]
|
||||
_ = x[LRCPC-160]
|
||||
_ = x[PMULL-161]
|
||||
_ = x[SHA1-162]
|
||||
_ = x[SHA2-163]
|
||||
_ = x[SHA3-164]
|
||||
_ = x[SHA512-165]
|
||||
_ = x[SM3-166]
|
||||
_ = x[SM4-167]
|
||||
_ = x[SVE-168]
|
||||
_ = x[lastID-169]
|
||||
_ = x[AMXFP16-6]
|
||||
_ = x[AMXINT8-7]
|
||||
_ = x[AMXTILE-8]
|
||||
_ = x[AVX-9]
|
||||
_ = x[AVX2-10]
|
||||
_ = x[AVX512BF16-11]
|
||||
_ = x[AVX512BITALG-12]
|
||||
_ = x[AVX512BW-13]
|
||||
_ = x[AVX512CD-14]
|
||||
_ = x[AVX512DQ-15]
|
||||
_ = x[AVX512ER-16]
|
||||
_ = x[AVX512F-17]
|
||||
_ = x[AVX512FP16-18]
|
||||
_ = x[AVX512IFMA-19]
|
||||
_ = x[AVX512PF-20]
|
||||
_ = x[AVX512VBMI-21]
|
||||
_ = x[AVX512VBMI2-22]
|
||||
_ = x[AVX512VL-23]
|
||||
_ = x[AVX512VNNI-24]
|
||||
_ = x[AVX512VP2INTERSECT-25]
|
||||
_ = x[AVX512VPOPCNTDQ-26]
|
||||
_ = x[AVXIFMA-27]
|
||||
_ = x[AVXNECONVERT-28]
|
||||
_ = x[AVXSLOW-29]
|
||||
_ = x[AVXVNNI-30]
|
||||
_ = x[AVXVNNIINT8-31]
|
||||
_ = x[BMI1-32]
|
||||
_ = x[BMI2-33]
|
||||
_ = x[CETIBT-34]
|
||||
_ = x[CETSS-35]
|
||||
_ = x[CLDEMOTE-36]
|
||||
_ = x[CLMUL-37]
|
||||
_ = x[CLZERO-38]
|
||||
_ = x[CMOV-39]
|
||||
_ = x[CMPCCXADD-40]
|
||||
_ = x[CMPSB_SCADBS_SHORT-41]
|
||||
_ = x[CMPXCHG8-42]
|
||||
_ = x[CPBOOST-43]
|
||||
_ = x[CPPC-44]
|
||||
_ = x[CX16-45]
|
||||
_ = x[EFER_LMSLE_UNS-46]
|
||||
_ = x[ENQCMD-47]
|
||||
_ = x[ERMS-48]
|
||||
_ = x[F16C-49]
|
||||
_ = x[FLUSH_L1D-50]
|
||||
_ = x[FMA3-51]
|
||||
_ = x[FMA4-52]
|
||||
_ = x[FP128-53]
|
||||
_ = x[FP256-54]
|
||||
_ = x[FSRM-55]
|
||||
_ = x[FXSR-56]
|
||||
_ = x[FXSROPT-57]
|
||||
_ = x[GFNI-58]
|
||||
_ = x[HLE-59]
|
||||
_ = x[HRESET-60]
|
||||
_ = x[HTT-61]
|
||||
_ = x[HWA-62]
|
||||
_ = x[HYBRID_CPU-63]
|
||||
_ = x[HYPERVISOR-64]
|
||||
_ = x[IA32_ARCH_CAP-65]
|
||||
_ = x[IA32_CORE_CAP-66]
|
||||
_ = x[IBPB-67]
|
||||
_ = x[IBRS-68]
|
||||
_ = x[IBRS_PREFERRED-69]
|
||||
_ = x[IBRS_PROVIDES_SMP-70]
|
||||
_ = x[IBS-71]
|
||||
_ = x[IBSBRNTRGT-72]
|
||||
_ = x[IBSFETCHSAM-73]
|
||||
_ = x[IBSFFV-74]
|
||||
_ = x[IBSOPCNT-75]
|
||||
_ = x[IBSOPCNTEXT-76]
|
||||
_ = x[IBSOPSAM-77]
|
||||
_ = x[IBSRDWROPCNT-78]
|
||||
_ = x[IBSRIPINVALIDCHK-79]
|
||||
_ = x[IBS_FETCH_CTLX-80]
|
||||
_ = x[IBS_OPDATA4-81]
|
||||
_ = x[IBS_OPFUSE-82]
|
||||
_ = x[IBS_PREVENTHOST-83]
|
||||
_ = x[IBS_ZEN4-84]
|
||||
_ = x[INT_WBINVD-85]
|
||||
_ = x[INVLPGB-86]
|
||||
_ = x[LAHF-87]
|
||||
_ = x[LAM-88]
|
||||
_ = x[LBRVIRT-89]
|
||||
_ = x[LZCNT-90]
|
||||
_ = x[MCAOVERFLOW-91]
|
||||
_ = x[MCDT_NO-92]
|
||||
_ = x[MCOMMIT-93]
|
||||
_ = x[MD_CLEAR-94]
|
||||
_ = x[MMX-95]
|
||||
_ = x[MMXEXT-96]
|
||||
_ = x[MOVBE-97]
|
||||
_ = x[MOVDIR64B-98]
|
||||
_ = x[MOVDIRI-99]
|
||||
_ = x[MOVSB_ZL-100]
|
||||
_ = x[MOVU-101]
|
||||
_ = x[MPX-102]
|
||||
_ = x[MSRIRC-103]
|
||||
_ = x[MSR_PAGEFLUSH-104]
|
||||
_ = x[NRIPS-105]
|
||||
_ = x[NX-106]
|
||||
_ = x[OSXSAVE-107]
|
||||
_ = x[PCONFIG-108]
|
||||
_ = x[POPCNT-109]
|
||||
_ = x[PPIN-110]
|
||||
_ = x[PREFETCHI-111]
|
||||
_ = x[PSFD-112]
|
||||
_ = x[RDPRU-113]
|
||||
_ = x[RDRAND-114]
|
||||
_ = x[RDSEED-115]
|
||||
_ = x[RDTSCP-116]
|
||||
_ = x[RTM-117]
|
||||
_ = x[RTM_ALWAYS_ABORT-118]
|
||||
_ = x[SERIALIZE-119]
|
||||
_ = x[SEV-120]
|
||||
_ = x[SEV_64BIT-121]
|
||||
_ = x[SEV_ALTERNATIVE-122]
|
||||
_ = x[SEV_DEBUGSWAP-123]
|
||||
_ = x[SEV_ES-124]
|
||||
_ = x[SEV_RESTRICTED-125]
|
||||
_ = x[SEV_SNP-126]
|
||||
_ = x[SGX-127]
|
||||
_ = x[SGXLC-128]
|
||||
_ = x[SHA-129]
|
||||
_ = x[SME-130]
|
||||
_ = x[SME_COHERENT-131]
|
||||
_ = x[SPEC_CTRL_SSBD-132]
|
||||
_ = x[SRBDS_CTRL-133]
|
||||
_ = x[SSE-134]
|
||||
_ = x[SSE2-135]
|
||||
_ = x[SSE3-136]
|
||||
_ = x[SSE4-137]
|
||||
_ = x[SSE42-138]
|
||||
_ = x[SSE4A-139]
|
||||
_ = x[SSSE3-140]
|
||||
_ = x[STIBP-141]
|
||||
_ = x[STIBP_ALWAYSON-142]
|
||||
_ = x[STOSB_SHORT-143]
|
||||
_ = x[SUCCOR-144]
|
||||
_ = x[SVM-145]
|
||||
_ = x[SVMDA-146]
|
||||
_ = x[SVMFBASID-147]
|
||||
_ = x[SVML-148]
|
||||
_ = x[SVMNP-149]
|
||||
_ = x[SVMPF-150]
|
||||
_ = x[SVMPFT-151]
|
||||
_ = x[SYSCALL-152]
|
||||
_ = x[SYSEE-153]
|
||||
_ = x[TBM-154]
|
||||
_ = x[TLB_FLUSH_NESTED-155]
|
||||
_ = x[TME-156]
|
||||
_ = x[TOPEXT-157]
|
||||
_ = x[TSCRATEMSR-158]
|
||||
_ = x[TSXLDTRK-159]
|
||||
_ = x[VAES-160]
|
||||
_ = x[VMCBCLEAN-161]
|
||||
_ = x[VMPL-162]
|
||||
_ = x[VMSA_REGPROT-163]
|
||||
_ = x[VMX-164]
|
||||
_ = x[VPCLMULQDQ-165]
|
||||
_ = x[VTE-166]
|
||||
_ = x[WAITPKG-167]
|
||||
_ = x[WBNOINVD-168]
|
||||
_ = x[X87-169]
|
||||
_ = x[XGETBV1-170]
|
||||
_ = x[XOP-171]
|
||||
_ = x[XSAVE-172]
|
||||
_ = x[XSAVEC-173]
|
||||
_ = x[XSAVEOPT-174]
|
||||
_ = x[XSAVES-175]
|
||||
_ = x[AESARM-176]
|
||||
_ = x[ARMCPUID-177]
|
||||
_ = x[ASIMD-178]
|
||||
_ = x[ASIMDDP-179]
|
||||
_ = x[ASIMDHP-180]
|
||||
_ = x[ASIMDRDM-181]
|
||||
_ = x[ATOMICS-182]
|
||||
_ = x[CRC32-183]
|
||||
_ = x[DCPOP-184]
|
||||
_ = x[EVTSTRM-185]
|
||||
_ = x[FCMA-186]
|
||||
_ = x[FP-187]
|
||||
_ = x[FPHP-188]
|
||||
_ = x[GPA-189]
|
||||
_ = x[JSCVT-190]
|
||||
_ = x[LRCPC-191]
|
||||
_ = x[PMULL-192]
|
||||
_ = x[SHA1-193]
|
||||
_ = x[SHA2-194]
|
||||
_ = x[SHA3-195]
|
||||
_ = x[SHA512-196]
|
||||
_ = x[SM3-197]
|
||||
_ = x[SM4-198]
|
||||
_ = x[SVE-199]
|
||||
_ = x[lastID-200]
|
||||
_ = x[firstID-0]
|
||||
}
|
||||
|
||||
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXSLOWAVXVNNIBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCX16ENQCMDERMSF16CFMA3FMA4FXSRFXSROPTGFNIHLEHRESETHTTHWAHYPERVISORIBPBIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_PREVENTHOSTINT_WBINVDINVLPGBLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCOMMITMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMPXMSRIRCMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTRDPRURDRANDRDSEEDRDTSCPRTMRTM_ALWAYS_ABORTSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTOPEXTTMETSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
||||
const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAVXAVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4INT_WBINVDINVLPGBLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRTMRTM_ALWAYS_ABORTSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"
|
||||
|
||||
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 58, 62, 72, 84, 92, 100, 108, 116, 123, 133, 143, 151, 161, 172, 180, 190, 208, 223, 230, 237, 241, 245, 251, 256, 264, 269, 275, 279, 297, 305, 312, 316, 322, 326, 330, 334, 338, 342, 349, 353, 356, 362, 365, 368, 378, 382, 385, 395, 406, 412, 420, 431, 439, 451, 467, 482, 492, 499, 503, 506, 513, 518, 529, 536, 539, 545, 550, 559, 566, 574, 577, 583, 596, 601, 603, 610, 617, 623, 628, 634, 640, 646, 649, 665, 674, 677, 686, 701, 714, 720, 734, 741, 744, 749, 752, 755, 767, 770, 774, 778, 782, 787, 792, 797, 802, 813, 819, 822, 827, 836, 840, 845, 850, 856, 863, 868, 871, 877, 880, 890, 898, 902, 911, 915, 927, 930, 940, 943, 950, 958, 961, 968, 971, 976, 982, 990, 996, 1002, 1010, 1015, 1022, 1029, 1037, 1044, 1049, 1054, 1061, 1065, 1067, 1071, 1074, 1079, 1084, 1089, 1093, 1097, 1101, 1107, 1110, 1113, 1116, 1122}
|
||||
var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 65, 69, 79, 91, 99, 107, 115, 123, 130, 140, 150, 158, 168, 179, 187, 197, 215, 230, 237, 249, 256, 263, 274, 278, 282, 288, 293, 301, 306, 312, 316, 325, 343, 351, 358, 362, 366, 380, 386, 390, 394, 403, 407, 411, 416, 421, 425, 429, 436, 440, 443, 449, 452, 455, 465, 475, 488, 501, 505, 509, 523, 540, 543, 553, 564, 570, 578, 589, 597, 609, 625, 639, 650, 660, 675, 683, 693, 700, 704, 707, 714, 719, 730, 737, 744, 752, 755, 761, 766, 775, 782, 790, 794, 797, 803, 816, 821, 823, 830, 837, 843, 847, 856, 860, 865, 871, 877, 883, 886, 902, 911, 914, 923, 938, 951, 957, 971, 978, 981, 986, 989, 992, 1004, 1018, 1028, 1031, 1035, 1039, 1043, 1048, 1053, 1058, 1063, 1077, 1088, 1094, 1097, 1102, 1111, 1115, 1120, 1125, 1131, 1138, 1143, 1146, 1162, 1165, 1171, 1181, 1189, 1193, 1202, 1206, 1218, 1221, 1231, 1234, 1241, 1249, 1252, 1259, 1262, 1267, 1273, 1281, 1287, 1293, 1301, 1306, 1313, 1320, 1328, 1335, 1340, 1345, 1352, 1356, 1358, 1362, 1365, 1370, 1375, 1380, 1384, 1388, 1392, 1398, 1401, 1404, 1407, 1413}
|
||||
|
||||
func (i FeatureID) String() string {
|
||||
if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
|
||||
|
|
|
|||
2
vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
generated
vendored
2
vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
generated
vendored
|
|
@ -83,7 +83,7 @@ func tryToFillCPUInfoFomSysctl(c *CPUInfo) {
|
|||
c.Model = sysctlGetInt(0, "machdep.cpu.model")
|
||||
c.CacheLine = sysctlGetInt64(0, "hw.cachelinesize")
|
||||
c.Cache.L1I = sysctlGetInt64(-1, "hw.l1icachesize")
|
||||
c.Cache.L1D = sysctlGetInt64(-1, "hw.l1icachesize")
|
||||
c.Cache.L1D = sysctlGetInt64(-1, "hw.l1dcachesize")
|
||||
c.Cache.L2 = sysctlGetInt64(-1, "hw.l2cachesize")
|
||||
c.Cache.L3 = sysctlGetInt64(-1, "hw.l3cachesize")
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue