mirror of
https://github.com/superseriousbusiness/gotosocial.git
synced 2025-11-03 14:12:25 -06:00
[feature] S3 support (#674)
* feat: vendor minio client * feat: introduce storage package with s3 support * feat: serve s3 files directly this saves a lot of bandwith as the files are fetched from the object store directly * fix: use explicit local storage in tests * feat: integrate s3 storage with the main server * fix: add s3 config to cli tests * docs: explicitly set values in example config also adds license header to the storage package * fix: use better http status code on s3 redirect HTTP 302 Found is the best fit, as it signifies that the resource requested was found but not under its presumed URL 307/TemporaryRedirect would mean that this resource is usually located here, not in this case 303/SeeOther indicates that the redirection does not link to the requested resource but to another page * refactor: use context in storage driver interface
This commit is contained in:
Dominik Süß
GitHub
parent
07b0a42b7f
commit
9d0df426da
250 changed files with 77798 additions and 185 deletions
219
vendor/github.com/klauspost/cpuid/detect_arm64.go
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vendor/github.com/klauspost/cpuid/detect_arm64.go
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// Copyright (c) 2015 Klaus Post, released under MIT License. See LICENSE file.
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//+build arm64,!gccgo,!noasm,!appengine
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package cpuid
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func getMidr() (midr uint64)
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func getProcFeatures() (procFeatures uint64)
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func getInstAttributes() (instAttrReg0, instAttrReg1 uint64)
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func initCPU() {
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cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
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cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
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xgetbv = func(uint32) (a, b uint32) { return 0, 0 }
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rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 }
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}
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func addInfo(c *CPUInfo) {
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// ARM64 disabled for now.
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if true {
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return
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}
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// midr := getMidr()
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// MIDR_EL1 - Main ID Register
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// x--------------------------------------------------x
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// | Name | bits | visible |
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// |--------------------------------------------------|
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// | Implementer | [31-24] | y |
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// |--------------------------------------------------|
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// | Variant | [23-20] | y |
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// |--------------------------------------------------|
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// | Architecture | [19-16] | y |
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// |--------------------------------------------------|
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// | PartNum | [15-4] | y |
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// |--------------------------------------------------|
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// | Revision | [3-0] | y |
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// x--------------------------------------------------x
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// fmt.Printf(" implementer: 0x%02x\n", (midr>>24)&0xff)
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// fmt.Printf(" variant: 0x%01x\n", (midr>>20)&0xf)
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// fmt.Printf("architecture: 0x%01x\n", (midr>>16)&0xf)
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// fmt.Printf(" part num: 0x%03x\n", (midr>>4)&0xfff)
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// fmt.Printf(" revision: 0x%01x\n", (midr>>0)&0xf)
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procFeatures := getProcFeatures()
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// ID_AA64PFR0_EL1 - Processor Feature Register 0
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// x--------------------------------------------------x
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// | Name | bits | visible |
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// |--------------------------------------------------|
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// | DIT | [51-48] | y |
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// |--------------------------------------------------|
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// | SVE | [35-32] | y |
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// |--------------------------------------------------|
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// | GIC | [27-24] | n |
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// |--------------------------------------------------|
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// | AdvSIMD | [23-20] | y |
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// |--------------------------------------------------|
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// | FP | [19-16] | y |
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// |--------------------------------------------------|
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// | EL3 | [15-12] | n |
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// |--------------------------------------------------|
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// | EL2 | [11-8] | n |
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// |--------------------------------------------------|
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// | EL1 | [7-4] | n |
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// |--------------------------------------------------|
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// | EL0 | [3-0] | n |
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// x--------------------------------------------------x
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var f ArmFlags
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// if procFeatures&(0xf<<48) != 0 {
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// fmt.Println("DIT")
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// }
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if procFeatures&(0xf<<32) != 0 {
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f |= SVE
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}
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if procFeatures&(0xf<<20) != 15<<20 {
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f |= ASIMD
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if procFeatures&(0xf<<20) == 1<<20 {
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// https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64pfr0_el1
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// 0b0001 --> As for 0b0000, and also includes support for half-precision floating-point arithmetic.
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f |= FPHP
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f |= ASIMDHP
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}
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}
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if procFeatures&(0xf<<16) != 0 {
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f |= FP
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}
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instAttrReg0, instAttrReg1 := getInstAttributes()
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// https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1
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//
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// ID_AA64ISAR0_EL1 - Instruction Set Attribute Register 0
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// x--------------------------------------------------x
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// | Name | bits | visible |
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// |--------------------------------------------------|
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// | TS | [55-52] | y |
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// |--------------------------------------------------|
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// | FHM | [51-48] | y |
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// |--------------------------------------------------|
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// | DP | [47-44] | y |
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// |--------------------------------------------------|
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// | SM4 | [43-40] | y |
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// |--------------------------------------------------|
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// | SM3 | [39-36] | y |
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// |--------------------------------------------------|
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// | SHA3 | [35-32] | y |
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// |--------------------------------------------------|
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// | RDM | [31-28] | y |
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// |--------------------------------------------------|
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// | ATOMICS | [23-20] | y |
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// |--------------------------------------------------|
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// | CRC32 | [19-16] | y |
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// |--------------------------------------------------|
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// | SHA2 | [15-12] | y |
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// |--------------------------------------------------|
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// | SHA1 | [11-8] | y |
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// |--------------------------------------------------|
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// | AES | [7-4] | y |
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// x--------------------------------------------------x
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// if instAttrReg0&(0xf<<52) != 0 {
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// fmt.Println("TS")
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// }
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// if instAttrReg0&(0xf<<48) != 0 {
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// fmt.Println("FHM")
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// }
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if instAttrReg0&(0xf<<44) != 0 {
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f |= ASIMDDP
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}
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if instAttrReg0&(0xf<<40) != 0 {
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f |= SM4
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}
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if instAttrReg0&(0xf<<36) != 0 {
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f |= SM3
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}
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if instAttrReg0&(0xf<<32) != 0 {
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f |= SHA3
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}
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if instAttrReg0&(0xf<<28) != 0 {
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f |= ASIMDRDM
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}
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if instAttrReg0&(0xf<<20) != 0 {
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f |= ATOMICS
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}
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if instAttrReg0&(0xf<<16) != 0 {
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f |= CRC32
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}
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if instAttrReg0&(0xf<<12) != 0 {
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f |= SHA2
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}
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if instAttrReg0&(0xf<<12) == 2<<12 {
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// https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1
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// 0b0010 --> As 0b0001, plus SHA512H, SHA512H2, SHA512SU0, and SHA512SU1 instructions implemented.
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f |= SHA512
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}
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if instAttrReg0&(0xf<<8) != 0 {
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f |= SHA1
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}
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if instAttrReg0&(0xf<<4) != 0 {
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f |= AES
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}
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if instAttrReg0&(0xf<<4) == 2<<4 {
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// https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar0_el1
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// 0b0010 --> As for 0b0001, plus PMULL/PMULL2 instructions operating on 64-bit data quantities.
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f |= PMULL
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}
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// https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64isar1_el1
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//
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// ID_AA64ISAR1_EL1 - Instruction set attribute register 1
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// x--------------------------------------------------x
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// | Name | bits | visible |
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// |--------------------------------------------------|
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// | GPI | [31-28] | y |
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// |--------------------------------------------------|
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// | GPA | [27-24] | y |
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// |--------------------------------------------------|
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// | LRCPC | [23-20] | y |
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// |--------------------------------------------------|
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// | FCMA | [19-16] | y |
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// |--------------------------------------------------|
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// | JSCVT | [15-12] | y |
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// |--------------------------------------------------|
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// | API | [11-8] | y |
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// |--------------------------------------------------|
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// | APA | [7-4] | y |
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// |--------------------------------------------------|
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// | DPB | [3-0] | y |
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// x--------------------------------------------------x
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// if instAttrReg1&(0xf<<28) != 0 {
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// fmt.Println("GPI")
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// }
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if instAttrReg1&(0xf<<28) != 24 {
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f |= GPA
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}
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if instAttrReg1&(0xf<<20) != 0 {
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f |= LRCPC
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}
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if instAttrReg1&(0xf<<16) != 0 {
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f |= FCMA
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}
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if instAttrReg1&(0xf<<12) != 0 {
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f |= JSCVT
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}
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// if instAttrReg1&(0xf<<8) != 0 {
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// fmt.Println("API")
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// }
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// if instAttrReg1&(0xf<<4) != 0 {
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// fmt.Println("APA")
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// }
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if instAttrReg1&(0xf<<0) != 0 {
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f |= DCPOP
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}
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c.Arm = f
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}
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