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644 lines
11 KiB
Go
644 lines
11 KiB
Go
// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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// Portions Copyright © 2019 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package riscv
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import "github.com/twitchyliquid64/golang-asm/obj"
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
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const (
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// Base register numberings.
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REG_X0 = obj.RBaseRISCV + iota
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REG_X1
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REG_X2
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REG_X3
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REG_X4
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REG_X5
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REG_X6
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REG_X7
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REG_X8
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REG_X9
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REG_X10
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REG_X11
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REG_X12
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REG_X13
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REG_X14
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REG_X15
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REG_X16
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REG_X17
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REG_X18
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REG_X19
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REG_X20
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REG_X21
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REG_X22
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REG_X23
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REG_X24
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REG_X25
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REG_X26
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REG_X27
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REG_X28
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REG_X29
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REG_X30
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REG_X31
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// FP register numberings.
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// This marks the end of the register numbering.
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REG_END
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// General registers reassigned to ABI names.
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REG_ZERO = REG_X0
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REG_RA = REG_X1 // aka REG_LR
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REG_SP = REG_X2
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REG_GP = REG_X3 // aka REG_SB
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REG_TP = REG_X4 // aka REG_G
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REG_T0 = REG_X5
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REG_T1 = REG_X6
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REG_T2 = REG_X7
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REG_S0 = REG_X8
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REG_S1 = REG_X9
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REG_A0 = REG_X10
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REG_A1 = REG_X11
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REG_A2 = REG_X12
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REG_A3 = REG_X13
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REG_A4 = REG_X14
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REG_A5 = REG_X15
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REG_A6 = REG_X16
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REG_A7 = REG_X17
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REG_S2 = REG_X18
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REG_S3 = REG_X19
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REG_S4 = REG_X20 // aka REG_CTXT
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REG_S5 = REG_X21
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REG_S6 = REG_X22
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REG_S7 = REG_X23
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REG_S8 = REG_X24
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REG_S9 = REG_X25
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REG_S10 = REG_X26
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REG_S11 = REG_X27
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REG_T3 = REG_X28
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REG_T4 = REG_X29
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REG_T5 = REG_X30
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REG_T6 = REG_X31 // aka REG_TMP
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// Go runtime register names.
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REG_G = REG_TP // G pointer.
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REG_CTXT = REG_S4 // Context for closures.
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REG_LR = REG_RA // Link register.
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REG_TMP = REG_T6 // Reserved for assembler use.
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// ABI names for floating point registers.
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REG_FT0 = REG_F0
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REG_FT1 = REG_F1
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REG_FT2 = REG_F2
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REG_FT3 = REG_F3
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REG_FT4 = REG_F4
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REG_FT5 = REG_F5
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REG_FT6 = REG_F6
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REG_FT7 = REG_F7
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REG_FS0 = REG_F8
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REG_FS1 = REG_F9
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REG_FA0 = REG_F10
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REG_FA1 = REG_F11
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REG_FA2 = REG_F12
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REG_FA3 = REG_F13
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REG_FA4 = REG_F14
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REG_FA5 = REG_F15
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REG_FA6 = REG_F16
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REG_FA7 = REG_F17
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REG_FS2 = REG_F18
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REG_FS3 = REG_F19
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REG_FS4 = REG_F20
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REG_FS5 = REG_F21
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REG_FS6 = REG_F22
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REG_FS7 = REG_F23
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REG_FS8 = REG_F24
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REG_FS9 = REG_F25
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REG_FS10 = REG_F26
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REG_FS11 = REG_F27
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REG_FT8 = REG_F28
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REG_FT9 = REG_F29
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REG_FT10 = REG_F30
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REG_FT11 = REG_F31
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// Names generated by the SSA compiler.
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REGSP = REG_SP
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REGG = REG_G
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)
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// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers
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var RISCV64DWARFRegisters = map[int16]int16{
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// Integer Registers.
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REG_X0: 0,
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REG_X1: 1,
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REG_X2: 2,
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REG_X3: 3,
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REG_X4: 4,
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REG_X5: 5,
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REG_X6: 6,
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REG_X7: 7,
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REG_X8: 8,
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REG_X9: 9,
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REG_X10: 10,
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REG_X11: 11,
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REG_X12: 12,
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REG_X13: 13,
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REG_X14: 14,
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REG_X15: 15,
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REG_X16: 16,
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REG_X17: 17,
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REG_X18: 18,
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REG_X19: 19,
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REG_X20: 20,
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REG_X21: 21,
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REG_X22: 22,
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REG_X23: 23,
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REG_X24: 24,
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REG_X25: 25,
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REG_X26: 26,
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REG_X27: 27,
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REG_X28: 28,
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REG_X29: 29,
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REG_X30: 30,
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REG_X31: 31,
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// Floating-Point Registers.
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REG_F0: 32,
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REG_F1: 33,
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REG_F2: 34,
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REG_F3: 35,
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REG_F4: 36,
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REG_F5: 37,
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REG_F6: 38,
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REG_F7: 39,
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REG_F8: 40,
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REG_F9: 41,
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REG_F10: 42,
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REG_F11: 43,
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REG_F12: 44,
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REG_F13: 45,
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REG_F14: 46,
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REG_F15: 47,
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REG_F16: 48,
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REG_F17: 49,
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REG_F18: 50,
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REG_F19: 51,
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REG_F20: 52,
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REG_F21: 53,
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REG_F22: 54,
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REG_F23: 55,
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REG_F24: 56,
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REG_F25: 57,
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REG_F26: 58,
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REG_F27: 59,
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REG_F28: 60,
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REG_F29: 61,
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REG_F30: 62,
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REG_F31: 63,
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}
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// Prog.Mark flags.
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const (
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// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
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// it is the first instruction in an AUIPC + I-type pair that needs a
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// R_RISCV_PCREL_ITYPE relocation.
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NEED_PCREL_ITYPE_RELOC = 1 << 0
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// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
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// it is the first instruction in an AUIPC + S-type pair that needs a
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// R_RISCV_PCREL_STYPE relocation.
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NEED_PCREL_STYPE_RELOC = 1 << 1
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)
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// RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
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// from:
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//
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// https://github.com/riscv/riscv-opcodes
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//
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// As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
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//
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// See also "The RISC-V Instruction Set Manual" at:
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//
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// https://riscv.org/specifications/
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//
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// If you modify this table, you MUST run 'go generate' to regenerate anames.go!
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const (
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// Unprivileged ISA (Document Version 20190608-Base-Ratified)
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// 2.4: Integer Computational Instructions
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AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
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ASLTI
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ASLTIU
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AANDI
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AORI
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AXORI
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ASLLI
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ASRLI
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ASRAI
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ALUI
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AAUIPC
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AADD
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ASLT
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ASLTU
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AAND
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AOR
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AXOR
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ASLL
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ASRL
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ASUB
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ASRA
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// The SLL/SRL/SRA instructions differ slightly between RV32 and RV64,
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// hence there are pseudo-opcodes for the RV32 specific versions.
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ASLLIRV32
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ASRLIRV32
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ASRAIRV32
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// 2.5: Control Transfer Instructions
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AJAL
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AJALR
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ABEQ
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ABNE
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ABLT
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ABLTU
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ABGE
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ABGEU
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// 2.6: Load and Store Instructions
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ALW
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ALWU
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ALH
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ALHU
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ALB
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ALBU
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ASW
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ASH
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ASB
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// 2.7: Memory Ordering Instructions
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AFENCE
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AFENCEI
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AFENCETSO
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// 5.2: Integer Computational Instructions (RV64I)
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AADDIW
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ASLLIW
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ASRLIW
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ASRAIW
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AADDW
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ASLLW
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ASRLW
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ASUBW
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ASRAW
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// 5.3: Load and Store Instructions (RV64I)
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ALD
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ASD
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// 7.1: Multiplication Operations
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AMUL
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AMULH
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AMULHU
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AMULHSU
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AMULW
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ADIV
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ADIVU
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AREM
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AREMU
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ADIVW
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ADIVUW
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AREMW
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AREMUW
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// 8.2: Load-Reserved/Store-Conditional Instructions
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ALRD
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ASCD
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ALRW
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ASCW
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// 8.3: Atomic Memory Operations
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AAMOSWAPD
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AAMOADDD
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AAMOANDD
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AAMOORD
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AAMOXORD
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AAMOMAXD
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AAMOMAXUD
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AAMOMIND
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AAMOMINUD
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AAMOSWAPW
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AAMOADDW
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AAMOANDW
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AAMOORW
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AAMOXORW
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AAMOMAXW
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AAMOMAXUW
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AAMOMINW
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AAMOMINUW
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// 10.1: Base Counters and Timers
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ARDCYCLE
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ARDCYCLEH
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ARDTIME
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ARDTIMEH
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ARDINSTRET
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ARDINSTRETH
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// 11.2: Floating-Point Control and Status Register
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AFRCSR
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AFSCSR
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AFRRM
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AFSRM
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AFRFLAGS
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AFSFLAGS
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AFSRMI
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AFSFLAGSI
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// 11.5: Single-Precision Load and Store Instructions
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AFLW
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AFSW
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// 11.6: Single-Precision Floating-Point Computational Instructions
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AFADDS
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AFSUBS
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AFMULS
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AFDIVS
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AFMINS
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AFMAXS
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AFSQRTS
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AFMADDS
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AFMSUBS
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AFNMADDS
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AFNMSUBS
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// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
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AFCVTWS
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AFCVTLS
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AFCVTSW
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AFCVTSL
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AFCVTWUS
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AFCVTLUS
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AFCVTSWU
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AFCVTSLU
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AFSGNJS
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AFSGNJNS
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AFSGNJXS
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AFMVXS
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AFMVSX
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AFMVXW
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AFMVWX
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// 11.8: Single-Precision Floating-Point Compare Instructions
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AFEQS
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AFLTS
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AFLES
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// 11.9: Single-Precision Floating-Point Classify Instruction
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AFCLASSS
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// 12.3: Double-Precision Load and Store Instructions
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AFLD
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AFSD
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// 12.4: Double-Precision Floating-Point Computational Instructions
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AFADDD
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AFSUBD
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AFMULD
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AFDIVD
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AFMIND
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AFMAXD
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AFSQRTD
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AFMADDD
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AFMSUBD
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AFNMADDD
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AFNMSUBD
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// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
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AFCVTWD
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AFCVTLD
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AFCVTDW
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AFCVTDL
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AFCVTWUD
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AFCVTLUD
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AFCVTDWU
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AFCVTDLU
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AFCVTSD
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AFCVTDS
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AFSGNJD
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AFSGNJND
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AFSGNJXD
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AFMVXD
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AFMVDX
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// 12.6: Double-Precision Floating-Point Compare Instructions
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AFEQD
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AFLTD
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AFLED
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// 12.7: Double-Precision Floating-Point Classify Instruction
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AFCLASSD
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// 13.1 Quad-Precision Load and Store Instructions
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AFLQ
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AFSQ
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// 13.2: Quad-Precision Computational Instructions
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AFADDQ
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AFSUBQ
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AFMULQ
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AFDIVQ
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AFMINQ
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AFMAXQ
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AFSQRTQ
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AFMADDQ
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AFMSUBQ
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AFNMADDQ
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AFNMSUBQ
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// 13.3 Quad-Precision Convert and Move Instructions
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AFCVTWQ
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AFCVTLQ
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AFCVTSQ
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AFCVTDQ
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AFCVTQW
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AFCVTQL
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AFCVTQS
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AFCVTQD
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AFCVTWUQ
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AFCVTLUQ
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AFCVTQWU
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AFCVTQLU
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AFSGNJQ
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AFSGNJNQ
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AFSGNJXQ
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AFMVXQ
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AFMVQX
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// 13.4 Quad-Precision Floating-Point Compare Instructions
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AFEQQ
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AFLEQ
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AFLTQ
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// 13.5 Quad-Precision Floating-Point Classify Instruction
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AFCLASSQ
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// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
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// 3.1.9: Instructions to Access CSRs
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ACSRRW
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ACSRRS
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ACSRRC
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ACSRRWI
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ACSRRSI
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ACSRRCI
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// 3.2.1: Environment Call and Breakpoint
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AECALL
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ASCALL
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AEBREAK
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ASBREAK
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// 3.2.2: Trap-Return Instructions
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AMRET
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ASRET
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AURET
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ADRET
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// 3.2.3: Wait for Interrupt
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AWFI
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// 4.2.1: Supervisor Memory-Management Fence Instruction
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ASFENCEVMA
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// Hypervisor Memory-Management Instructions
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AHFENCEGVMA
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AHFENCEVVMA
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// The escape hatch. Inserts a single 32-bit word.
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AWORD
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// Pseudo-instructions. These get translated by the assembler into other
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// instructions, based on their operands.
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ABEQZ
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ABGEZ
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ABGT
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ABGTU
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|
ABGTZ
|
|
ABLE
|
|
ABLEU
|
|
ABLEZ
|
|
ABLTZ
|
|
ABNEZ
|
|
AFNEGD
|
|
AFNEGS
|
|
AFNED
|
|
AFNES
|
|
AMOV
|
|
AMOVB
|
|
AMOVBU
|
|
AMOVF
|
|
AMOVD
|
|
AMOVH
|
|
AMOVHU
|
|
AMOVW
|
|
AMOVWU
|
|
ANEG
|
|
ANEGW
|
|
ANOT
|
|
ASEQZ
|
|
ASNEZ
|
|
|
|
// End marker
|
|
ALAST
|
|
)
|
|
|
|
// All unary instructions which write to their arguments (as opposed to reading
|
|
// from them) go here. The assembly parser uses this information to populate
|
|
// its AST in a semantically reasonable way.
|
|
//
|
|
// Any instructions not listed here are assumed to either be non-unary or to read
|
|
// from its argument.
|
|
var unaryDst = map[obj.As]bool{
|
|
ARDCYCLE: true,
|
|
ARDCYCLEH: true,
|
|
ARDTIME: true,
|
|
ARDTIMEH: true,
|
|
ARDINSTRET: true,
|
|
ARDINSTRETH: true,
|
|
}
|
|
|
|
// Instruction encoding masks.
|
|
const (
|
|
// ITypeImmMask is a mask including only the immediate portion of
|
|
// I-type instructions.
|
|
ITypeImmMask = 0xfff00000
|
|
|
|
// STypeImmMask is a mask including only the immediate portion of
|
|
// S-type instructions.
|
|
STypeImmMask = 0xfe000f80
|
|
|
|
// UTypeImmMask is a mask including only the immediate portion of
|
|
// U-type instructions.
|
|
UTypeImmMask = 0xfffff000
|
|
|
|
// UJTypeImmMask is a mask including only the immediate portion of
|
|
// UJ-type instructions.
|
|
UJTypeImmMask = UTypeImmMask
|
|
)
|