mirror of
https://github.com/superseriousbusiness/gotosocial.git
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1033 lines
15 KiB
Go
1033 lines
15 KiB
Go
// cmd/7c/7.out.h from Vita Nuova.
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// https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package arm64
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import "github.com/twitchyliquid64/golang-asm/obj"
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const (
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NSNAME = 8
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NSYM = 50
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NREG = 32 /* number of general registers */
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NFREG = 32 /* number of floating point registers */
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)
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// General purpose registers, kept in the low bits of Prog.Reg.
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const (
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// integer
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REG_R0 = obj.RBaseARM64 + iota
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REG_R1
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REG_R2
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REG_R3
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REG_R4
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REG_R5
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REG_R6
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REG_R7
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_R16
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REG_R17
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REG_R18
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REG_R19
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REG_R20
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REG_R21
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REG_R22
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REG_R23
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REG_R24
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REG_R25
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REG_R26
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REG_R27
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REG_R28
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REG_R29
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REG_R30
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REG_R31
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// scalar floating point
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// SIMD
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REG_V0
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REG_V1
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REG_V2
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REG_V3
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REG_V4
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REG_V5
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REG_V6
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REG_V7
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REG_V8
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REG_V9
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REG_V10
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REG_V11
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REG_V12
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REG_V13
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REG_V14
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REG_V15
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REG_V16
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REG_V17
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REG_V18
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REG_V19
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REG_V20
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REG_V21
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REG_V22
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REG_V23
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REG_V24
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REG_V25
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REG_V26
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REG_V27
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REG_V28
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REG_V29
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REG_V30
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REG_V31
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// The EQ in
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// CSET EQ, R0
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// is encoded as TYPE_REG, even though it's not really a register.
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COND_EQ
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COND_NE
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COND_HS
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COND_LO
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COND_MI
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COND_PL
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COND_VS
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COND_VC
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COND_HI
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COND_LS
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COND_GE
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COND_LT
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COND_GT
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COND_LE
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COND_AL
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COND_NV
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REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
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)
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// bits 0-4 indicates register: Vn
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// bits 5-8 indicates arrangement: <T>
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const (
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REG_ARNG = obj.RBaseARM64 + 1<<10 + iota<<9 // Vn.<T>
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REG_ELEM // Vn.<T>[index]
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REG_ELEM_END
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)
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// Not registers, but flags that can be combined with regular register
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// constants to indicate extended register conversion. When checking,
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// you should subtract obj.RBaseARM64 first. From this difference, bit 11
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// indicates extended register, bits 8-10 select the conversion mode.
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// REG_LSL is the index shift specifier, bit 9 indicates shifted offset register.
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const REG_LSL = obj.RBaseARM64 + 1<<9
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const REG_EXT = obj.RBaseARM64 + 1<<11
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const (
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REG_UXTB = REG_EXT + iota<<8
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REG_UXTH
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REG_UXTW
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REG_UXTX
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REG_SXTB
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REG_SXTH
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REG_SXTW
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REG_SXTX
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)
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// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
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// a special register and the low bits select the register.
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// SYSREG_END is the last item in the automatically generated system register
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// declaration, and it is defined in the sysRegEnc.go file.
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const (
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REG_SPECIAL = obj.RBaseARM64 + 1<<12
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REG_DAIFSet = SYSREG_END + iota
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REG_DAIFClr
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REG_PLDL1KEEP
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REG_PLDL1STRM
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REG_PLDL2KEEP
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REG_PLDL2STRM
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REG_PLDL3KEEP
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REG_PLDL3STRM
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REG_PLIL1KEEP
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REG_PLIL1STRM
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REG_PLIL2KEEP
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REG_PLIL2STRM
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REG_PLIL3KEEP
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REG_PLIL3STRM
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REG_PSTL1KEEP
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REG_PSTL1STRM
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REG_PSTL2KEEP
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REG_PSTL2STRM
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REG_PSTL3KEEP
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REG_PSTL3STRM
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)
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// Register assignments:
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//
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// compiler allocates R0 up as temps
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// compiler allocates register variables R7-R25
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// compiler allocates external registers R26 down
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//
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// compiler allocates register variables F7-F26
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// compiler allocates external registers F26 down
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const (
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REGMIN = REG_R7 // register variables allocated from here to REGMAX
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REGRT1 = REG_R16 // ARM64 IP0, external linker may use as a scrach register in trampoline
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REGRT2 = REG_R17 // ARM64 IP1, external linker may use as a scrach register in trampoline
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REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain
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REGMAX = REG_R25
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REGCTXT = REG_R26 // environment for closures
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REGTMP = REG_R27 // reserved for liblink
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REGG = REG_R28 // G
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REGFP = REG_R29 // frame pointer, unused in the Go toolchain
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REGLINK = REG_R30
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// ARM64 uses R31 as both stack pointer and zero register,
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// depending on the instruction. To differentiate RSP from ZR,
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// we use a different numeric value for REGZERO and REGSP.
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REGZERO = REG_R31
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REGSP = REG_RSP
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FREGRET = REG_F0
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FREGMIN = REG_F7 // first register variable
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FREGMAX = REG_F26 // last register variable for 7g only
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FREGEXT = REG_F26 // first external register
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)
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// http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf
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var ARM64DWARFRegisters = map[int16]int16{
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REG_R0: 0,
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REG_R1: 1,
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REG_R2: 2,
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REG_R3: 3,
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REG_R4: 4,
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REG_R5: 5,
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REG_R6: 6,
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REG_R7: 7,
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REG_R8: 8,
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REG_R9: 9,
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REG_R10: 10,
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REG_R11: 11,
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REG_R12: 12,
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REG_R13: 13,
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REG_R14: 14,
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REG_R15: 15,
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REG_R16: 16,
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REG_R17: 17,
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REG_R18: 18,
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REG_R19: 19,
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REG_R20: 20,
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REG_R21: 21,
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REG_R22: 22,
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REG_R23: 23,
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REG_R24: 24,
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REG_R25: 25,
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REG_R26: 26,
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REG_R27: 27,
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REG_R28: 28,
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REG_R29: 29,
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REG_R30: 30,
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// floating point
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REG_F0: 64,
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REG_F1: 65,
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REG_F2: 66,
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REG_F3: 67,
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REG_F4: 68,
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REG_F5: 69,
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REG_F6: 70,
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REG_F7: 71,
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REG_F8: 72,
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REG_F9: 73,
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REG_F10: 74,
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REG_F11: 75,
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REG_F12: 76,
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REG_F13: 77,
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REG_F14: 78,
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REG_F15: 79,
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REG_F16: 80,
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REG_F17: 81,
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REG_F18: 82,
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REG_F19: 83,
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REG_F20: 84,
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REG_F21: 85,
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REG_F22: 86,
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REG_F23: 87,
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REG_F24: 88,
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REG_F25: 89,
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REG_F26: 90,
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REG_F27: 91,
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REG_F28: 92,
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REG_F29: 93,
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REG_F30: 94,
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REG_F31: 95,
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// SIMD
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REG_V0: 64,
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REG_V1: 65,
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REG_V2: 66,
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REG_V3: 67,
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REG_V4: 68,
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REG_V5: 69,
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REG_V6: 70,
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REG_V7: 71,
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REG_V8: 72,
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REG_V9: 73,
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REG_V10: 74,
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REG_V11: 75,
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REG_V12: 76,
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REG_V13: 77,
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REG_V14: 78,
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REG_V15: 79,
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REG_V16: 80,
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REG_V17: 81,
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REG_V18: 82,
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REG_V19: 83,
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REG_V20: 84,
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REG_V21: 85,
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REG_V22: 86,
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REG_V23: 87,
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REG_V24: 88,
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REG_V25: 89,
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REG_V26: 90,
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REG_V27: 91,
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REG_V28: 92,
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REG_V29: 93,
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REG_V30: 94,
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REG_V31: 95,
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}
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const (
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BIG = 2048 - 8
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)
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const (
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/* mark flags */
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LABEL = 1 << iota
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LEAF
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FLOAT
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BRANCH
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LOAD
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FCMP
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SYNC
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LIST
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FOLL
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NOSCHED
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)
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const (
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// optab is sorted based on the order of these constants
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// and the first match is chosen.
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// The more specific class needs to come earlier.
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C_NONE = iota
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C_REG // R0..R30
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C_RSP // R0..R30, RSP
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C_FREG // F0..F31
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C_VREG // V0..V31
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C_PAIR // (Rn, Rm)
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C_SHIFT // Rn<<2
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C_EXTREG // Rn.UXTB[<<3]
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C_SPR // REG_NZCV
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C_COND // EQ, NE, etc
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C_ARNG // Vn.<T>
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C_ELEM // Vn.<T>[index]
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C_LIST // [V1, V2, V3]
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C_ZCON // $0 or ZR
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C_ABCON0 // could be C_ADDCON0 or C_BITCON
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C_ADDCON0 // 12-bit unsigned, unshifted
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C_ABCON // could be C_ADDCON or C_BITCON
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C_AMCON // could be C_ADDCON or C_MOVCON
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C_ADDCON // 12-bit unsigned, shifted left by 0 or 12
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C_MBCON // could be C_MOVCON or C_BITCON
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C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
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C_BITCON // bitfield and logical immediate masks
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C_ADDCON2 // 24-bit constant
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C_LCON // 32-bit constant
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C_MOVCON2 // a constant that can be loaded with one MOVZ/MOVN and one MOVK
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C_MOVCON3 // a constant that can be loaded with one MOVZ/MOVN and two MOVKs
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C_VCON // 64-bit constant
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C_FCON // floating-point constant
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C_VCONADDR // 64-bit memory address
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C_AACON // ADDCON offset in auto constant $a(FP)
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C_AACON2 // 24-bit offset in auto constant $a(FP)
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C_LACON // 32-bit offset in auto constant $a(FP)
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C_AECON // ADDCON offset in extern constant $e(SB)
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// TODO(aram): only one branch class should be enough
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C_SBRA // for TYPE_BRANCH
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C_LBRA
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C_ZAUTO // 0(RSP)
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C_NSAUTO_8 // -256 <= x < 0, 0 mod 8
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C_NSAUTO_4 // -256 <= x < 0, 0 mod 4
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C_NSAUTO // -256 <= x < 0
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C_NPAUTO // -512 <= x < 0, 0 mod 8
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C_NAUTO4K // -4095 <= x < 0
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C_PSAUTO_8 // 0 to 255, 0 mod 8
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C_PSAUTO_4 // 0 to 255, 0 mod 4
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C_PSAUTO // 0 to 255
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C_PPAUTO // 0 to 504, 0 mod 8
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C_UAUTO4K_8 // 0 to 4095, 0 mod 8
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C_UAUTO4K_4 // 0 to 4095, 0 mod 4
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C_UAUTO4K_2 // 0 to 4095, 0 mod 2
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C_UAUTO4K // 0 to 4095
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C_UAUTO8K_8 // 0 to 8190, 0 mod 8
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C_UAUTO8K_4 // 0 to 8190, 0 mod 4
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C_UAUTO8K // 0 to 8190, 0 mod 2
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C_UAUTO16K_8 // 0 to 16380, 0 mod 8
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C_UAUTO16K // 0 to 16380, 0 mod 4
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C_UAUTO32K // 0 to 32760, 0 mod 8
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C_LAUTO // any other 32-bit constant
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C_SEXT1 // 0 to 4095, direct
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C_SEXT2 // 0 to 8190
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C_SEXT4 // 0 to 16380
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C_SEXT8 // 0 to 32760
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C_SEXT16 // 0 to 65520
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C_LEXT
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C_ZOREG // 0(R)
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C_NSOREG_8 // must mirror C_NSAUTO_8, etc
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C_NSOREG_4
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C_NSOREG
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C_NPOREG
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C_NOREG4K
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C_PSOREG_8
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C_PSOREG_4
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C_PSOREG
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C_PPOREG
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C_UOREG4K_8
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C_UOREG4K_4
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C_UOREG4K_2
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C_UOREG4K
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C_UOREG8K_8
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C_UOREG8K_4
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C_UOREG8K
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C_UOREG16K_8
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C_UOREG16K
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C_UOREG32K
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C_LOREG
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C_ADDR // TODO(aram): explain difference from C_VCONADDR
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// The GOT slot for a symbol in -dynlink mode.
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C_GOTADDR
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// TLS "var" in local exec mode: will become a constant offset from
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// thread local base that is ultimately chosen by the program linker.
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C_TLS_LE
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// TLS "var" in initial exec mode: will become a memory address (chosen
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// by the program linker) that the dynamic linker will fill with the
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// offset from the thread local base.
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C_TLS_IE
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C_ROFF // register offset (including register extended)
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C_GOK
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C_TEXTSIZE
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C_NCLASS // must be last
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)
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const (
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C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
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C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
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)
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
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|
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const (
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AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
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AADCS
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AADCSW
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AADCW
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AADD
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AADDS
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AADDSW
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AADDW
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AADR
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AADRP
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AAND
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AANDS
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AANDSW
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AANDW
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AASR
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AASRW
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AAT
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ABFI
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ABFIW
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ABFM
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ABFMW
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ABFXIL
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ABFXILW
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ABIC
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ABICS
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ABICSW
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ABICW
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ABRK
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ACBNZ
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ACBNZW
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ACBZ
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|
ACBZW
|
|
ACCMN
|
|
ACCMNW
|
|
ACCMP
|
|
ACCMPW
|
|
ACINC
|
|
ACINCW
|
|
ACINV
|
|
ACINVW
|
|
ACLREX
|
|
ACLS
|
|
ACLSW
|
|
ACLZ
|
|
ACLZW
|
|
ACMN
|
|
ACMNW
|
|
ACMP
|
|
ACMPW
|
|
ACNEG
|
|
ACNEGW
|
|
ACRC32B
|
|
ACRC32CB
|
|
ACRC32CH
|
|
ACRC32CW
|
|
ACRC32CX
|
|
ACRC32H
|
|
ACRC32W
|
|
ACRC32X
|
|
ACSEL
|
|
ACSELW
|
|
ACSET
|
|
ACSETM
|
|
ACSETMW
|
|
ACSETW
|
|
ACSINC
|
|
ACSINCW
|
|
ACSINV
|
|
ACSINVW
|
|
ACSNEG
|
|
ACSNEGW
|
|
ADC
|
|
ADCPS1
|
|
ADCPS2
|
|
ADCPS3
|
|
ADMB
|
|
ADRPS
|
|
ADSB
|
|
AEON
|
|
AEONW
|
|
AEOR
|
|
AEORW
|
|
AERET
|
|
AEXTR
|
|
AEXTRW
|
|
AHINT
|
|
AHLT
|
|
AHVC
|
|
AIC
|
|
AISB
|
|
ALDADDAB
|
|
ALDADDAD
|
|
ALDADDAH
|
|
ALDADDAW
|
|
ALDADDALB
|
|
ALDADDALD
|
|
ALDADDALH
|
|
ALDADDALW
|
|
ALDADDB
|
|
ALDADDD
|
|
ALDADDH
|
|
ALDADDW
|
|
ALDADDLB
|
|
ALDADDLD
|
|
ALDADDLH
|
|
ALDADDLW
|
|
ALDANDAB
|
|
ALDANDAD
|
|
ALDANDAH
|
|
ALDANDAW
|
|
ALDANDALB
|
|
ALDANDALD
|
|
ALDANDALH
|
|
ALDANDALW
|
|
ALDANDB
|
|
ALDANDD
|
|
ALDANDH
|
|
ALDANDW
|
|
ALDANDLB
|
|
ALDANDLD
|
|
ALDANDLH
|
|
ALDANDLW
|
|
ALDAR
|
|
ALDARB
|
|
ALDARH
|
|
ALDARW
|
|
ALDAXP
|
|
ALDAXPW
|
|
ALDAXR
|
|
ALDAXRB
|
|
ALDAXRH
|
|
ALDAXRW
|
|
ALDEORAB
|
|
ALDEORAD
|
|
ALDEORAH
|
|
ALDEORAW
|
|
ALDEORALB
|
|
ALDEORALD
|
|
ALDEORALH
|
|
ALDEORALW
|
|
ALDEORB
|
|
ALDEORD
|
|
ALDEORH
|
|
ALDEORW
|
|
ALDEORLB
|
|
ALDEORLD
|
|
ALDEORLH
|
|
ALDEORLW
|
|
ALDORAB
|
|
ALDORAD
|
|
ALDORAH
|
|
ALDORAW
|
|
ALDORALB
|
|
ALDORALD
|
|
ALDORALH
|
|
ALDORALW
|
|
ALDORB
|
|
ALDORD
|
|
ALDORH
|
|
ALDORW
|
|
ALDORLB
|
|
ALDORLD
|
|
ALDORLH
|
|
ALDORLW
|
|
ALDP
|
|
ALDPW
|
|
ALDPSW
|
|
ALDXR
|
|
ALDXRB
|
|
ALDXRH
|
|
ALDXRW
|
|
ALDXP
|
|
ALDXPW
|
|
ALSL
|
|
ALSLW
|
|
ALSR
|
|
ALSRW
|
|
AMADD
|
|
AMADDW
|
|
AMNEG
|
|
AMNEGW
|
|
AMOVK
|
|
AMOVKW
|
|
AMOVN
|
|
AMOVNW
|
|
AMOVZ
|
|
AMOVZW
|
|
AMRS
|
|
AMSR
|
|
AMSUB
|
|
AMSUBW
|
|
AMUL
|
|
AMULW
|
|
AMVN
|
|
AMVNW
|
|
ANEG
|
|
ANEGS
|
|
ANEGSW
|
|
ANEGW
|
|
ANGC
|
|
ANGCS
|
|
ANGCSW
|
|
ANGCW
|
|
ANOOP
|
|
AORN
|
|
AORNW
|
|
AORR
|
|
AORRW
|
|
APRFM
|
|
APRFUM
|
|
ARBIT
|
|
ARBITW
|
|
AREM
|
|
AREMW
|
|
AREV
|
|
AREV16
|
|
AREV16W
|
|
AREV32
|
|
AREVW
|
|
AROR
|
|
ARORW
|
|
ASBC
|
|
ASBCS
|
|
ASBCSW
|
|
ASBCW
|
|
ASBFIZ
|
|
ASBFIZW
|
|
ASBFM
|
|
ASBFMW
|
|
ASBFX
|
|
ASBFXW
|
|
ASDIV
|
|
ASDIVW
|
|
ASEV
|
|
ASEVL
|
|
ASMADDL
|
|
ASMC
|
|
ASMNEGL
|
|
ASMSUBL
|
|
ASMULH
|
|
ASMULL
|
|
ASTXR
|
|
ASTXRB
|
|
ASTXRH
|
|
ASTXP
|
|
ASTXPW
|
|
ASTXRW
|
|
ASTLP
|
|
ASTLPW
|
|
ASTLR
|
|
ASTLRB
|
|
ASTLRH
|
|
ASTLRW
|
|
ASTLXP
|
|
ASTLXPW
|
|
ASTLXR
|
|
ASTLXRB
|
|
ASTLXRH
|
|
ASTLXRW
|
|
ASTP
|
|
ASTPW
|
|
ASUB
|
|
ASUBS
|
|
ASUBSW
|
|
ASUBW
|
|
ASVC
|
|
ASXTB
|
|
ASXTBW
|
|
ASXTH
|
|
ASXTHW
|
|
ASXTW
|
|
ASYS
|
|
ASYSL
|
|
ATBNZ
|
|
ATBZ
|
|
ATLBI
|
|
ATST
|
|
ATSTW
|
|
AUBFIZ
|
|
AUBFIZW
|
|
AUBFM
|
|
AUBFMW
|
|
AUBFX
|
|
AUBFXW
|
|
AUDIV
|
|
AUDIVW
|
|
AUMADDL
|
|
AUMNEGL
|
|
AUMSUBL
|
|
AUMULH
|
|
AUMULL
|
|
AUREM
|
|
AUREMW
|
|
AUXTB
|
|
AUXTH
|
|
AUXTW
|
|
AUXTBW
|
|
AUXTHW
|
|
AWFE
|
|
AWFI
|
|
AYIELD
|
|
AMOVB
|
|
AMOVBU
|
|
AMOVH
|
|
AMOVHU
|
|
AMOVW
|
|
AMOVWU
|
|
AMOVD
|
|
AMOVNP
|
|
AMOVNPW
|
|
AMOVP
|
|
AMOVPD
|
|
AMOVPQ
|
|
AMOVPS
|
|
AMOVPSW
|
|
AMOVPW
|
|
ASWPAD
|
|
ASWPAW
|
|
ASWPAH
|
|
ASWPAB
|
|
ASWPALD
|
|
ASWPALW
|
|
ASWPALH
|
|
ASWPALB
|
|
ASWPD
|
|
ASWPW
|
|
ASWPH
|
|
ASWPB
|
|
ASWPLD
|
|
ASWPLW
|
|
ASWPLH
|
|
ASWPLB
|
|
ABEQ
|
|
ABNE
|
|
ABCS
|
|
ABHS
|
|
ABCC
|
|
ABLO
|
|
ABMI
|
|
ABPL
|
|
ABVS
|
|
ABVC
|
|
ABHI
|
|
ABLS
|
|
ABGE
|
|
ABLT
|
|
ABGT
|
|
ABLE
|
|
AFABSD
|
|
AFABSS
|
|
AFADDD
|
|
AFADDS
|
|
AFCCMPD
|
|
AFCCMPED
|
|
AFCCMPS
|
|
AFCCMPES
|
|
AFCMPD
|
|
AFCMPED
|
|
AFCMPES
|
|
AFCMPS
|
|
AFCVTSD
|
|
AFCVTDS
|
|
AFCVTZSD
|
|
AFCVTZSDW
|
|
AFCVTZSS
|
|
AFCVTZSSW
|
|
AFCVTZUD
|
|
AFCVTZUDW
|
|
AFCVTZUS
|
|
AFCVTZUSW
|
|
AFDIVD
|
|
AFDIVS
|
|
AFLDPD
|
|
AFLDPS
|
|
AFMOVD
|
|
AFMOVS
|
|
AFMOVQ
|
|
AFMULD
|
|
AFMULS
|
|
AFNEGD
|
|
AFNEGS
|
|
AFSQRTD
|
|
AFSQRTS
|
|
AFSTPD
|
|
AFSTPS
|
|
AFSUBD
|
|
AFSUBS
|
|
ASCVTFD
|
|
ASCVTFS
|
|
ASCVTFWD
|
|
ASCVTFWS
|
|
AUCVTFD
|
|
AUCVTFS
|
|
AUCVTFWD
|
|
AUCVTFWS
|
|
AWORD
|
|
ADWORD
|
|
AFCSELS
|
|
AFCSELD
|
|
AFMAXS
|
|
AFMINS
|
|
AFMAXD
|
|
AFMIND
|
|
AFMAXNMS
|
|
AFMAXNMD
|
|
AFNMULS
|
|
AFNMULD
|
|
AFRINTNS
|
|
AFRINTND
|
|
AFRINTPS
|
|
AFRINTPD
|
|
AFRINTMS
|
|
AFRINTMD
|
|
AFRINTZS
|
|
AFRINTZD
|
|
AFRINTAS
|
|
AFRINTAD
|
|
AFRINTXS
|
|
AFRINTXD
|
|
AFRINTIS
|
|
AFRINTID
|
|
AFMADDS
|
|
AFMADDD
|
|
AFMSUBS
|
|
AFMSUBD
|
|
AFNMADDS
|
|
AFNMADDD
|
|
AFNMSUBS
|
|
AFNMSUBD
|
|
AFMINNMS
|
|
AFMINNMD
|
|
AFCVTDH
|
|
AFCVTHS
|
|
AFCVTHD
|
|
AFCVTSH
|
|
AAESD
|
|
AAESE
|
|
AAESIMC
|
|
AAESMC
|
|
ASHA1C
|
|
ASHA1H
|
|
ASHA1M
|
|
ASHA1P
|
|
ASHA1SU0
|
|
ASHA1SU1
|
|
ASHA256H
|
|
ASHA256H2
|
|
ASHA256SU0
|
|
ASHA256SU1
|
|
ASHA512H
|
|
ASHA512H2
|
|
ASHA512SU0
|
|
ASHA512SU1
|
|
AVADD
|
|
AVADDP
|
|
AVAND
|
|
AVBIF
|
|
AVCMEQ
|
|
AVCNT
|
|
AVEOR
|
|
AVMOV
|
|
AVLD1
|
|
AVLD2
|
|
AVLD3
|
|
AVLD4
|
|
AVLD1R
|
|
AVLD2R
|
|
AVLD3R
|
|
AVLD4R
|
|
AVORR
|
|
AVREV16
|
|
AVREV32
|
|
AVREV64
|
|
AVST1
|
|
AVST2
|
|
AVST3
|
|
AVST4
|
|
AVDUP
|
|
AVADDV
|
|
AVMOVI
|
|
AVUADDLV
|
|
AVSUB
|
|
AVFMLA
|
|
AVFMLS
|
|
AVPMULL
|
|
AVPMULL2
|
|
AVEXT
|
|
AVRBIT
|
|
AVUSHR
|
|
AVUSHLL
|
|
AVUSHLL2
|
|
AVUXTL
|
|
AVUXTL2
|
|
AVUZP1
|
|
AVUZP2
|
|
AVSHL
|
|
AVSRI
|
|
AVBSL
|
|
AVBIT
|
|
AVTBL
|
|
AVZIP1
|
|
AVZIP2
|
|
AVCMTST
|
|
ALAST
|
|
AB = obj.AJMP
|
|
ABL = obj.ACALL
|
|
)
|
|
|
|
const (
|
|
// shift types
|
|
SHIFT_LL = 0 << 22
|
|
SHIFT_LR = 1 << 22
|
|
SHIFT_AR = 2 << 22
|
|
)
|
|
|
|
// Arrangement for ARM64 SIMD instructions
|
|
const (
|
|
// arrangement types
|
|
ARNG_8B = iota
|
|
ARNG_16B
|
|
ARNG_1D
|
|
ARNG_4H
|
|
ARNG_8H
|
|
ARNG_2S
|
|
ARNG_4S
|
|
ARNG_2D
|
|
ARNG_1Q
|
|
ARNG_B
|
|
ARNG_H
|
|
ARNG_S
|
|
ARNG_D
|
|
)
|